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Q24 turns off the motor when -POR B is asserted or when the micro-
processor causes DICEY to deassert -SPIN, which turns off Q8.
Back
EMF generated by the spinning motor flows through the IC drivers,
whose outputs are clamped to 6 V, producing dynamic braking.
2.3.3
Electronic Return Spring
When the drive is powered down, the electronic return spring utilizes
the back EMF from the slowing motor, switching it to the actuator,
thus forcing the headstack into the landing zone.
At power-on-reset, -POR turns Q3 off after a delay set by C29.
This
delay allows the driver currents to fall to a safe level (while Q5
discharges C36 and clamps the U8 current integrator output).
Q4, Q7,
and Q14 turn on.
Twice per revolution Q7 passes current from the
motor to the actuator, then through Q14 and R42 to ground.
If the +12 V dc supply has failed, the circuit still functions, but if
the +12 V dc is maintained, more current is supplied to the actuator.
Only milliseconds are required to move the actuator into the landing
zone; AIRLOCK operates about 30 seconds later.
Do not handle the
drive during this period.
2.3.4
5080 SCSI Bus Controller
A 5080 SCSI Controller IC is used to implement the SCSI interface.
CMOS technology reduces the power consumption.
All inputs and outputs
conform to standard 5 V logic levels.
The SCSI bus pins of the 5080
meet the ANSI standards, and are connected directly to the SCSI bus.
The 5080 can operate with various microprocessors; in this application
it is strapped to operate with an 8031 or 8032 by tying the CONFIG pin
low and the IOEN pin high.
Pins XOR A7-A5 are strapped so the 5080 is
selected when address bits MAD7-5 are 110 (address range CO - DF).
On command of the microprocessor, the 5080 reads the SCSI address of
the drive and the options set by the shorting plugs, which are con-
nected to 5080 pins IN 0-5.
Figure 2-10 is a conceptual block diagram of the 5080.
Figure 2-11
emphasizes the external interfaces.
The signals mentioned below are
shown on the schematics in SECTION 3 and in Figure 2-4.
Registers in the 5080 are written and read by the microprocessor
over the MAD bus.
In this way, for example, the microprocessor can
(1) switch the 5080 from target to initiator mode,
(2) assert and
deassert SCSI bus signals,
(3) read the state of SCSI bus control sig-
nals from the host, and (4) set the programmable timing for the SCSI
SELECTION/ RESELECTION and ARBITRATION phases.
The 5080 provides
logic for arbitration.
2-21
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