Table of Contents
Advertisement
o
Asserts +READ GATE to indicate when data should be processed
through the read data synchronizer.
o
Asserts +PREVLD to indicate to DICEY that a valid preamble
should be present.
o
Asserts +QUAL ERR to indicate to the microprocessor and
DICEY that the wedge area does not meet the qualification
criteria, which are: (1) sector and echo pulses appear at
the correct times, and (2) no pulses are detected in the
three dc erase fields.
Note: to avoid overwriting the servo tracks, writing is
inhibited in a wedge.
Moreover, the microprocessor inhibits
writing data in the sector if QUAL ERR is asserted.
Several variations of the crystal oscillator circuits have been manu-
factured; the PCB accomodates either (1) a 12 MHz crystal driven by
the microprocessor, with a 15 MHz crystal and associated driver IC in
a metal can at U25, or (2) a dual- frequency 12 MHz and 15 MHz crystal
oscillator module with driver ICs in a metal can at U25.
AND gate
(pins 3 - 6) in U23 is required only for option (1).
2.3.9
DICEY Data Controller IC
DICEY is a custom data controller IC, a 100-pin device proprietary to
Quantum and designed by Quantum for the Q200 series disk drives.
See
U14 on the schematics in SECTION 3 for the pinout and Figure 2-14 for
the block diagram.
All pins conform to standard 5 V logic levels.
DICEY performs several functions, listed below, including miscel-
laneous "glue logic," thereby significantly reducing the number of
chips on the PCB, and improving the drive reliability.
DICEY has these features:
o
Controlled by microprocessor, which communicates with DICEY
over the MAD bus.
o
Microprocessor sees DICEY as a set of 34 registers to which
it can write to control data transfer, or read to determine
status, etc.
o
Performs serial-to-parallel and parallel-to-serial
conversions.
o
Encodes all data written to disk and decodes all data read
from the disk, using a 2/3 RLL (1,7) code.
The notation
means that the code maps two data bits into three code bits,
2-30
Advertisement
Table of Contents
