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PlL HI 811
1IA DATA
AD DATA
AD CLOCK
PRE VLD
IF
ADDAIDATA
UTCI£D
ADDA.DUT
AUX
I/O
BUS
DICEY IC
..
SERIAL CHANNEL
III
RESISTER
11
BUS
I
I
11
-
--
UP
..
INTERFACE
-"""
.....
,
MASTER
CONTROL
UNIT
..
-
•
,
DMA
CONTROLLER
-
-
BlFFEA
DATA
BlFFER
AIlIlA.
BlFFER
CONTROLS
SCSI
INTEIFACE
Figure 2-14: DICEY Block Diagram
and that the encoded bit stream has between one and seven
o
bits between each 1 bit.
o
Generates a sync time-out error if sync is not detected
after pll locks on the preamble (an alternating field of Is
and Os).
o
Detects sync pattern (100100) and generates a sync error if
there is a drop out, drop in, or shifted bit.
o
Controls access to buffer RAM via DMA transfers, in this
priority: (1) disk, including user data and servo position
data,
(2) microprocessor, and (3) 5080 SCSI controller.
o
DMA cycles are controlled by a state machine in the Master
Control Unit, synchronized to the 15 MHz clock from FYLO.
o
Disk and write functions are controlled by a state machine
in the serial channel, synchronized to READ CLOCK.
o
Can read and write to buffer RAM (to and from both the disk
and the SCSI bus) at the burst transfer rate of 1.25 Mbytesj
sec.
2-31
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