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The AGC circuit samples the filtered differential signal, and controls
the U2 (A) amplifier gain to keep the average peak-to- peak amplitude
constant (actually, four times the voltage applied to VREF).
C9 and
R9 set the averaging time constant so the gain decreases rapidly for
high peak signal amplitudes and increases more slowly when the signal
amplitude is low.
+ENC DA T A ---+.---J
+RD ClK
Figure 2-13: Read Circuit Waveforms
Each signal peak corresponds to a magnetic transition written on the
disk.
The 8464 first differentiates the filtered signal to convert
the peaks to zero crossings with a high rate of change of voltage with
time, easily detected.
Noise pulses are suppressed by qualifying the
zero crossings: to qualify, they must be caused by alternating posi-
tive and negative peaks of the filtered, but undifferentiated signal
that exceed the level set by VHYS.
Qualified zero crossings trigger a
one-shot, producing a pulse for each signal peak.
This is the output
signal, +RAW DATA.
C7 sets the pulse width, and R1, Cl set the dif-
ferentiation time constant.
When no data is being read, AND gate U23 (pin 12) keeps the U1 PLL
output (+RD CLK) locked to the 15 MHz clock input, thus reducing the
PLL synchronization time.
FYLO predicts a preamble and asserts +READ
GATE twice per sector: once at the A burst preamble, and again at the
user data preamble.
FYLO asserts +PREVLD whenever the head should be
over a valid preamble, and DICEY then asserts +PLL HBW to hold the PLL
in a high gain tracking mode and allow fast phase lock onto +ENCODED
DATA, which is buffered +RAW DATA.
Later, while track following,
DICEY de-asserts +PLL HBW for lower PLL gain and less jitter.
As the preamble is being read, +READ CLK quickly synchronizes to the
positive-going transitions of +ENCODED DATA.
DICEY strobes +RD DATA
with +READ CLK to determine which bit cells contain encoded data
2-28
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