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pulses, and then transforms this data from
2/3
RLL (1,7) encoded data
to an a-bit data byte.
The byte is passed from DICEY to buffer RAM in
a DMA transfer.
R17, RIB, C20, and C21 set the PLL gain and bandwidth.
C22 sets the
VCO frequency, and R21 the VCO operating current.
C17,
C1B,
and R20
set the PLL loop bandwidth and damping, and integrate the PLL charge
pump current.
R19, C15, and C16 compensate for phase shift, and are
selected for the 10 Mbit/sec data rate.
write
See the description of the Flex Circuit, section
2.2.B,
for an outline
of write circuit operation.
In write mode, data received by the
50BO
SCSI Controller is stored in RAM and passed to DICEY via DMA.
DICEY
encodes the data from its B-bit form to a serial stream of
2/3
RLL
(1,7) coded data.
DICEY asserts -WR GATE when it detects a user area, thereby switching
the flex circuit chip from preamplifier to write driver.
U20 contains
six non-inverting buffers, used to improve signal immunity to noise:
the inputs are 1A - 6A; the corresponding outputs are 1Y - 6Y.
write current in the head is proportional to the current from WRITE
CURRENT to ground.
The microprocessor compensates for the lower
output of the outer tracks: through DICEY, it asserts AUX 5, turning
on Q21, inserting R22 in parallel with R23 and thus increasing WRITE
CURRENT.
On a reset, POR B turns off Q22, reducing WRITE CURRENT to
near zero.
2.3.B
FYLO Timing Controller IC, and Xtal Oscillators
FYLO is a custom IC proprietary to Quantum that incorporates a number
of timing functions.
See device U9 on the schematics in SECTION 3 for
the pinout.
FYLO performs the following functions:
o
Accepts +RAW DATA, and buffers the signal to produce
+ENCODED DATA.
o
Derives the 2 MHz clock from the 12 MHz clock, and buffers
the 2 MHz, 12MHz, and 15 MHz clocks.
o
Outputs -WEDGE to identify the wedge area.
o
Controls the servo AMC sample and hold timing with outputs
-RST AMP and +HOLD.
o
Begins servo-burst AID conversion by asserting -CONVERT.
2-29
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