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Refer to the schematic diagrams in SECTION 3, and the waveforms in
Figures 2-12, 5-1, 5-2 and 5-3.
The differential signal from the AGC
amplifier is +READ SIG and -READ SIG.
Transistors (1, 2, 3, and 5, 4,
3) in transistor array U11 full-wave rectify the signal and convert it
to a proportional current, which is mirrored by Q17 and Q18.
Tran-
sistor (6, 7, 8) in U11 sinks the mirrored current when no burst is
present.
At the beginning of a burst, -RST AMP is asserted, which turns off U11
transistor (12, 13, 14).
In turn, this biases Q20 on and discharges
C72, initializing the sample and hold integrator U12 (pins 5,
6,
7).
During the preamble period of a burst, FYLO deasserts -RST AMP, allow-
ing current from the current mirror to flow through CR5 and charge
C72.
The charge accumulates during an integral number of cycles of
the preamble signal, until FYLO asserts +HOLD and turns on Q19, sink-
ing the current that would otherwise flow through CR5.
BURST PEAK, the output of U12 (pin 7), is now a voltage inversely pro-
portional to the charge on C72, and thus to the burst amplitude.
When
FYLO asserts -CONVERT, the AMC DAC converts this voltage to an 8-bit
number.
The microprocessor places it on the MAD bus by causing DICEY
to assert -ADC RD.
Burst Amplitude
Maximum
Zero
U12 Integrator Output
2.5 volts
3.7
Servo AGC Circuit Description
U10 ADC Output
o
(decimal)
255
Follow this explanation on the schematics in SECTION 3.
To control the Servo AGC, the microprocessor selects AGC DAC U28 by
placing 8 bits corresponding to the desired Servo AGC on the MAD bus,
strobes the bits into the DAC with -DAC CS and -WR, and asserts +AGC
DAC.
The U12 (pins 1, 2, 3) op-amp output is 3.7 to 7.4 volts for
°
to 255 (decimal) DAC input.
The DAC output is divided and becomes the
input to Q10, an emitter follower.
Transistor array U27 is switched
on when -WEDGE is asserted, and then mirrors the current from Q10 and
converts it to a high-current output.
This output connects to CAGC,
and overrides the CAGC signal produced by pulse detector U2 (B).
Therefore, the Servo AGC sets the U2 (A) amplifier gain when reading
bursts, but the U2 (B) circuit sets the amplifier gain when reading
data from the user areas.
2-26
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