Pll Circuits - Icom ID-1 Service Manual

and then mixed with the amplified I/Q baseband signals. The
modulated signal is output from pin 14.
The modulated signal (IC890, pin 14) is passed through the
bandpass (FI880) and low-pass (L892, L893, C904–C908)
filters and then applied to the 1st mixer circuit.
• FM MODE
The modulation circuit modulates the 2nd LO signal using
the microphone audio signals.
The switched AF signals from the mode switch (IC1673, pin
6) change the reactance of varactor diode (D631) to modu-
late the 2nd LO signal at the 2nd VCO circuit (Q631, D630).
The modulated signal from the 2nd VCO circuit is amplified
at the buffer amplifiers (Q632, Q771) and is then applied to
the T/R switch (D770). The switched signal is applied to the
2nd LO amplifier (Q890) and then passed through the low-
pass filter (L891, C896–C898), quadrature modulator IC
(IC890), bandpass filter (FI880) and low-pass filter (L892,
L893, C904–C908).
The filtered signal is applied to the 1st mixer circuit.
4-2-4 1ST MIXER CIRCUITS (MAIN UNIT)
The filtered signal from the low-pass filter (L892, L893, C904
–C908) is mixed with the 1st LO signal, generated at the
1st VCO circuit (Q471, Q472, D472) via the buffer amplifier
(Q710), at the 1st mixer circuit (IC960, pin 1, 6) to convert
into the RF signal. The RF signal from the 1st mixer circuit
(IC960, pin 6) is passed through the bandpass fi lter (FI961)
and then amplifi ed at the RF amplifi er (IC1021). The ampli-
fi ed signal is passed through the bandpass fi lter (FI1020) to
suppress spurious components.
4-2-5 DRIVE/POWER AMPLIFIER CIRCUITS
(MAIN UNIT)
The filtered RF signal from the bandpass filter (FI1020) is
amplifi ed at the drive (Q1080, Q1081) and power (IC1160)
amplifi ers to obtain a stable 10 W of output power.

• PLL CIRCUITS

IC551
Analog
switch
Loop Loop
filter
filter
Loop
filter
Buffer
Q400
Q632
2nd VCO
Buffer
Q631, D630
IC550
LPF
PLL IC
1st VCO
Buffer
Q473
Q471, Q472,
D472
IC400
LPF
PLL IC
15.3 MHz
The power amplifi ed signal from the power amplifi er (IC1160,
pin 4) is passed through the antenna switch (D1160),
SWR detector circuit (D1166, D1170), low-pass fi lter which
contains strip-line and C1198, and then applied to the
antenna connector (CHASSIS unit: J1).
4-2-6 APC CIRCUIT (MAIN UNIT)
The APC circuit protects the driver and power amplifiers
from a mismatched output load and stabilizes the output
power.
The SWR detector circuit (D1166, D1170) detects the for-
ward signals and reflection signals, and converts it into DC
voltage. The output voltage is at a minimum level when the
antenna impedance is matched with 50 Ω and is increased
when it is mismatched.
The detected voltage is applied to the APC amplifier (IC1250,
pins 3, 4) and is compared with the reference voltage which
is supplied from the CPU (LOGIC-1 unit: IC50, pin 38) as
"PCON" signal.
When antenna impedance is mismatched, the detected volt-
age exceeds the power setting voltage. The output voltage
of the APC amplifiers (IC1250, IC1251) controls the bias
voltage of the drive (Q1080) and power (IC1160) amplifiers
to reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUITS (MAIN UNIT)
The PLL circuit provides stable oscillation of the 1st LO fre-
quencies and 2nd LO frequency. The PLL output compares
the phase of the divided VCO frequency to the reference
frequency. The PLL output frequency is controlled by the
divided ratio (N-data) of a programmable divider.
4-3-2 1ST PLL CIRCUIT (MAIN UNIT)
The 1st PLL circuit oscillates the 1st LO frequencies, and
signals are applied to the 1st mixer circuit. The oscillated
Q771
D770
Buffer
Buffer
Q633
D771
2ND PLL CIRCUIT
1ST PLL CIRCUIT
D710
Q710
Buffer
Buffer
Q474
D711
X400
4 - 5
to 2nd LO amplifier
to 2nd mixer circuit
to 1st mixer circuit
to 1st mixer circuit