Pll Circuits - Icom IC-M87 Service Manual

The amplified signal is passed through the low-pass filter
(L121, L122, C121, C122), power detector (D121), antenna
switching circuit (D131) and another low-pass filter (L131,
L132, C132-C136).
The filtered signal is applied to the antenna connector
(CHASSIS unit; J1).
4-2-4 APC CIRCUIT (MAIN UNIT)
The APC circuit stabilizes transmit power and selects output
power of HIGH or LOW.
The power detector circuit (D121) detects the transmit power
output level and converts it into DC voltage.
The detected voltage is applied to the APC amplifi er (IC141,
pin 3) and is compared with the reference voltage that is sup-
plied from the CPU (LOGIC unit: IC166) as "T1CON" signal
via the D/A converter (IC251, pin 14).
The output voltage from the APC amplifier (IC141, pin 4)
controls the bias voltage of the buffer (Q91), drive (Q101)
and power (Q111) amplifi ers to control the output power by
comparing the detected voltage and reference voltage.
• APC CIRCUIT
VCC
T5V
RF signal
from PLL circuit
"T1CON" signal from the D/A
convertor IC (IC251, pin 14)
"TXMS" signal from the
expander IC (IC341, pin 12)
S5V
• PLL CIRCUIT
Loop
filter
"2nd LO" signal (30.6 MHz)
to the FM IF IC (IC231, pin 2)
X1
15.3 MHz
Buffer
amp.
1
4
Q141 IC141
3
APC amplifier
RX VCO
Q41, D31 D34
TX VCO
Q51, D35 D38
Phase
5 Programmable
detector counter
2 Programmable
2
divider
1

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the RX VCO (Q41, D31–D34) and
TX VCO (Q51, D35–D38). The oscillated signal is amplifi ed
at the buffer amplifi ers (Q61, Q71) and then applied to the
PLL IC (IC1, pin 8) after being passed through the low-pass
fi lter (L72, C74, C75).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The applied
signal is divided at the prescaler and programmable coun-
ter section by the N-data ratio from the CPU (LOGIC unit;
IC661).
The reference signal is generated at the reference oscillator
(X1) and is applied to the PLL IC (IC1). The PLL IC detects
the out-of-step phase using the reference frequency and out-
puts it from pin 5 (IC1). The output signal is passed thorough
the loop fi lter and is then applied to the VCO circuit as the
lock voltage.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
Q91 Q101
Power
Drive
amp.
amp.
D91
Buffer
Q62
Buffer
Q61
D92
Buffer
Q71
8
Prescaler
11
PLSTBO
10
Shift register SDATAO
9
SCLKO
IC1
MA15A02PFV1
4 - 3
Q111 D131
ANT
LPF
SW
Power detector
circuit (D121)
"TDETV" to the CPU
(LOGIC unit; IC661, pin 31)
to transmitter circuit
to the 1st mixer circuit
LPF
to antenna