Pll Circuits - Icom IC-2710H Service Manual

4-3 PLL CIRCUITS

GENERAL
4-3-1
A PLL circuit provides stable oscillation of the transmit
frequency and the receive local frequen
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by a crystal oscillator and the divided ratio of the program­
mable divider.
4-3-2 VHF PLL CIRCUITS
V-VHF LOOP
The generated signal at the V-VHF VCO (018, 019) is
amplified at the buffer-amplifiers (017, 040) and then
applied to the PLL IC (IC6 pin 19).
divided by serial data from the CPU and phase-detected
with the divided reference frequency. The phase difference
is output as pulses.
The output signal from IC6 (pin 13) is converted to DC
voltages (lock voltage) by the active loop filter (041-043)
and then fed back to the V-VHF VCO circuit to stabilize the
VCO frequency.
The lock voltage is also used for the receiver circuit for
tracking the bandpass filter center frequency.
voltage from 042 is amplified at the buffer-amplifier (035)
and then applied to the VHF RF circuit.
V-UHF LOOP
This loop is used for UHF receiver in VHF display while the
U/U para-watch function is activated.
The generated signal at the V-UHF VCO (033) is amplified
at the buffer-amplifiers (032, 040) and then applied to the
PLL IC (IC6 pin 19). The applied signals are divided by
serial data from the CPU and phase-detected with the
divided reference frequency.
output as pulses.
The output signal from IC6 (pin 13) is converted to DC
voltages (lock voltage) by the active loop filter (041-043)
and then fed back to the V-UHF VCO circuit to stabilize the
VCO frequency.
VHF PLL CIRCUIT
to UHF PLL IC (IC12 pin 16)
Reference osc.
X1 (12.8 MHz)
CLK
Shift register
DATA
STROBE
'
cy. The PLL circuit
The applied signal is
The lock
The phase difference is
to VHF RF circuit
19
Prescaler
IC6 µPD3140GS
4 - 4
4-3-3 UHF PLL CIRCUITS
U-UHF LOOP
The generated signal at the U-UHF VCO (0123) is
amplified at the buffer-amplifiers (0122, 0130) and then
applied to the PLL IC (IC12 pin 19).
are divided by serial data from the CPU and phase-detected
with the divided reference frequency. The phase difference
is output as pulses.
The output signal from IC12 (pin 13) is converted to DC
voltages (lock voltage) by the active loop filter (0131-0133)
and then fed back to the U-UHF VCO circuit to stabilize the
VCO frequency.
U-VHF LOOP
This loop is used for VHF receiver in UHF display while the
VN para-watch function is activated.
The generated signal at the U-VHF VCO (0113, 0114) is
amplified at the buffer-amplifiers (0112, 0130) and then
applied to the PLL IC (IC12 pin 19).
are divided by serial data from the CPU and phase-detected
with the divided reference frequency. The phase difference
is output as pulses.
The output signal from IC12 (pin 13) is converted to DC
voltages (lock voltage) by the active loop filter (0131-0133)
and then fed back to the U-VHF VCO circuit to stabilize the
VCO frequency.
The lock voltage is also used for the receiver circuit for
tracking the bandpass filter center frequency.
voltage from 0132 is amplified at buffer amplifiers (0140)
and then applied to the VHF circuit.
r-----,
V-VHFVCO
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I I
- - - - - -·
018, 019, 015
The applied signals
The applied signals
The lock
to V-VHF LO switch
to V-UHF mixer
031, 030