Pll Circuits - Icom IC-F4029TDR Service Manual Addendum

4-3 PLL CIRCUITS

4-3-1 VCO
VCO is a oscillator whose oscillating frequency is controlled
by adding voltage (lock voltage).
This transceiver has 2 VCO's; RX VCO (Q17, D9, D11) and
TX VCO (Q16, D10, D13). The RX VCO oscillates the 1st LO
signals, and the TX VCO oscillates the transmit signal.
• RX VCO
The output signals are amplified by the buffer amplifiers
(Q15, Q29), and applied to the 1st mixer (Q6) via TX/RX
switch (D16 is OFF, D17 is ON) and LPF (L12, L46, C46,
C47, C396, C397), to be mixed with the received signals to
produce the 46.35 MHz 1st IF signal.
• TX VCO
The output signal is applied to the transmit amplifi ers via the
buffer amplifi ers (Q15, Q29) and TX/RX switch (D16 is ON,
D17 is OFF).
A portion of each VCO output is applied to the PLL IC (IC2,
pin 8) via the buffer amplifi er (Q15), doubler (Q14) and the
BPF (L32, L34, C196, C197, C205).
• PLL CIRCUIT
5
Loop
filter
7
PLL unlock signal
to the CPU (IC22, pin 34)
TX VCO
Q16, D10, D13
RX VCO
Q17, D9, D10
Charge Programmable
pump
divider
Phase
Shift register
detector
Reference
counter
4-3-2 PLL IC
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL output
frequency is controlled by the divided ratio (N-data) from the
CPU.
The VCO output signals from the BPF (L32, L34, C196,
C197, C205) are applied to the PLL IC (IC2, pin 8).
The applied signals are divided at the prescaler and
programmable counter according to the "SSO" signal from the
CPU (IC22, pin 99). The divided signal is phase-compared
with the reference frequency signal from the reference
frequency oscillator (X2), at the phase detector.
The phase difference is output from pin 5 as a pulse type
signal after being passed through the internal charge pump.
The output signal is converted into the DC voltage (lock
voltage) by passing through the loop filter (R94−R96, C16,
C17, C146). The lock voltage is applied to the varactors (D9
and D11 of RX VCO, D10 and D13 of TX VCO) and locked to
keep the VCO frequency constant.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the VCO oscillating frequency.
Buffer
Q29
Buffer
Q15
×2
Q14
PLL IC (IC2)
8
Prescaler BPF
9
SCK
10
SSO
PLL control signals from the CPU (IC22)
11
PLST
15.3 MHz
1
reference frequency signal
4 - 4
D16
to transmitter circuits
D17
to 1st IF circuits
TCXO
X2