Pll Circuits - Icom IC-F24/S Service Manual Addendum

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation for the transmit fre-
quency and the receive 1st LO frequency. The PLL output
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX/RX VCO circuits (TX:
Q13, D17, D18, D21; RX: Q14, D16, D22). The oscillated
signal is amplified at the buffer amplifiers (Q11, Q12) and
then applied to the PLL IC (IC4, pin 8) after being passed
through the low-pass filter (L32, C206, C208).
The PLL IC (IC4) contains a prescaler, programmable
counter, programmable divider and phase detector, charge
pump, etc. The entered signal is divided at the prescaler and
programmable counter section by the N-data ratio from the
CPU. The divided signal is detected on phase at the phase
detector using the reference frequency. The phase detected
signal is applied to the charge pump to be converted into
the DC voltage, and output from pin 5. After passes through
the loop filter (C130, C138, C146, C147, R95–R97), the DC
voltage is applied to the TX/RX VCO as the lock voltage.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
• PLL CIRCUITS
Buffer
Q18
"LVIN" signal to the CPU
(IC13, pin 64)
45.9 MHz 2nd LO
signal to the FM IF IC
Tripler
(IC1, pin 2)
Q19
RX VCO
Q14, D16, D22
TX VCO
Q13, D17, D21
Loop
filter
5 Phase
Charge
detector
pump
Programmable
divider
2
3
4-3-2 VCO CIRCUITS
The VCO circuit contains a separate RX VCO (Q14, D16,
D22) and TX VCO (Q13, D17, D21). The oscillated signal
is amplified at the buffer amplifiers (Q10, Q12) and is then
applied to the T/R switch (D14 for TX, D15 for RX). Then the
receive 1st LO (RX) signal is applied to the 1st mixer circuit
(Q3) and the transmit (TX) signal to the pre-drive amplifier
(Q9).
A portion of the signal from the buffer amplifier (Q12) is fed
back to the PLL IC (IC4, pin 8) via the buffer amplifier (Q11)
and low-pass filter (L32, C206, C208) as the comparison
signal.
Buffer
Q10
Buffer
Q12
Buffer
Q11
IC4 MB15A02
Programm-
Prescaler
able counter
Shift register
1
X2
15.3 MHz
4 - 4
D15
to 1st mixer circuit
D14
to transmitter circuit
LPF
8
9
CLOCK
10
DATA
11
PLST