Schematic Diagram - Fpga Dsp Board (3/3) - Sony HAP-S1 Service Manual

5-21. SCHEMATIC DIAGRAM - FPGA DSP Board (3/3) -

1 2 3
FPGA DSP BOARD
A
B
C
D
DATA_IN_CIRRUS
LRCLK_OUT_CIRRUS
BCLK_OUT_CIRRUS
DATA_OUT
LRCLK_OUT
BCLK_OUT
E
R701
0
F CIRRUS_CORE_1.2V
R702
0
>132S
CIRRUS_3.3V
FPGA DSP
BOARD
(1/3)
GND
(Page 59)
VDD_3.3V
G
H
I
HAP-S1
• See page 73 for Waveforms. • See page 86 for IC Pin Function Description.
4 5 6 7
(3/3)
C704 C707
0.1 0.1
23
24
R703
10
CL701 0 19 12
IC702
DAO_D1 nRESET
R704 10 CL702 1.6 20 11
DAO_LRCLK nINT/HS1
R705 10 CL703 21 AUDIO DSP 10
1.6
DAO_SCLK nBUSY/HS0/nEE_CS
IC702
R706 10 CL704
0 22 9
CS48L10-CNZR
DAI_D1 MOSI
R707 10 CL705
1.6 23 8
DAI_LRCLK MISO/SDA
CL706
1.6 24 7
DAI_SCLK nCS
R708
10
25
26
22
C702 C701 C703 C705 C708
10 10 0.1 0.1 0.1
R709
22 IC701
CLOCK BUFFER 21
IC701
TC7WHU04FK
1 8 3.3
VCC
1.6 2 7
CL709
1.5 3 6 1.6
4 5 1.6
GND
R710
X701 R712
1M
6MHz 3.3k FB701
8 9 10
C710
0.01
R714 R716 R718
10k 10k 10k
22M_OE
24M_OE
R720
100
3 CL711 RST_DSP
3.2 CL712 R721 22 DATAL_DSDLD
3.2 CL713 R722 22 DATAR_DSDRD
CL714 R723 22
0 SDO_DSP
CL715 R724 22
3.2 SDI_DSP
CL716 R725 22
3.2 128FS_IN
SDK_DSP
CS_DAC
SDO_DAC
SDK_DAC
R719
22
R713
2.2k
BCLK_OUT
LRCLK_OUT
C706 C709
0.01 0.1
DATA_OUT
DATA_IN_CIRRUS
R532
10
61 61
11 12 13 14
IC001 (4/4)
FPGA
CSP
(Chip Size Package)
IC001
EP4CGX30BF14C8N
BANK 3
N4
CL501
IO/DIFFIO_B1P/CRC_ERROR IO/PLL1_CLKOUTP
N5
IO/DIFFIO_B1N/NCEO IO/PLL1_CLKOUTN
L5
IO/DQS1B/CQ0B#/DPCLK2
L7
IO/VREFB3N0 IO/DIFFIO_B3N/DQ0B
BANK 4
N8
IO/DIFFIO_B12P/DQ0B IO/PLL3_CLKOUTP
N9
IO/DIFFIO_B12N/DQ0B IO/PLL3_CLKOUTN
K8
IO/VREFB4N0 IO/DIFFIO_B19P/DQ0B
K9
IO/DQ0B IO/DIFFIO_B19N/DQS0B/CQ0B/DPCLK5
M11
IO/RUP2/DQ0B IO/DIFFIO_B21P/DQ0B
N12
IO/RDN2/DM0B IO/DIFFIO_B21N/DQ0B
R581
10k
M7
CLK14/DIFFCLK_6P
N7
CLK15/DIFFCLK_6N
R582
10k
R512 BANK 5
10
H10
IO/DQS1R/CQ0R#/DPCLK7 IO/DIFFIO_R9N/DQ0R
R513 10 H12
IO/VREFB5N0 IO/DIFFIO_R9P/DQ0R
R514
IO/DIFFIO_R13P/DQ0R
220 FB501
N13
IO/RUP3 IO/DIFFIO_R13N/DQ0R
R515 100 M13
IO/RDN3 IO/DIFFIO_R14P/DQ0R
R580
IO/DIFFIO_R14N/DQ0R
10k
H13
CLK5/DIFFCLK_2P
CL520
G13
CLK4/DIFFCLK_2N
R518
820
R519 BANK 6
10
D11
IO/DIFFIO_R2P IO/DIFFIO_R5P/DQ0R
R520 10
D12
IO/DIFFIO_R2N IO/DIFFIO_R5N/DQ0R
R521 10
E10
IO/DIFFIO_R4P/DM0R IO/DIFFIO_R6P/DQS0R/CQ0R/DPCLK8
F9
IO_F9 IO/DIFFIO_R6N/DEV_OE
CL502
R522 E13
10 IO/VREFB6N0
R523
10
F12
CLK7/DIFFCLK_3P
F13
CLK6/DIFFCLK_3N
R524
10
BANK 7
A12
R526
IO/DIFFIO_T11P/DM0T IO/DIFFIO_T12P/DQ0T
10
A11
IO/DIFFIO_T11N/DQ0T IO/DIFFIO_T12N/DQ0T
R527 10
B11
IO_B11 IO/DIFFIO_T17P/DQ0T
B10
IO/VREFB7N0 IO/DIFFIO_T17N/DQS0T/CQ0T/DPCLK10
R528 C11
10 IO/RUP4/DQ0T IO/DIFFIO_T18P/DQ0T
C12
IO/RDN4/DQ0T IO/DIFFIO_T18N/DQ0T
R531
10 CL521
A10
CLK9/DIFFCLK_5P
CL522
A9
CLK8/DIFFCLK_5N
BANK 8
A6
IO/CLKUSR IO/PLL2_CLKOUTP
R570 R534 B6
10k 10 IO/DQS1T/CQ0T#/DPCLK13 IO/PLL2_CLKOUTN
C6
IO/VREFB8N0
BANK 9
CL503
C5
IO/NCSO NC_N2
CL504
B5
IO/ASDO NC_M3
Note: IC001 and IC702 on the FPGA DSP board cannot exchange with single.
HAP-S1
15 16 17 18
CN506
24P
1 DIRGND
CL505
DATAR_DSDRD
2 L
3 DIRGND
CL506
DATAL_DSDLD
4 BCLK_L
5 DIRGND
CL507
WDCKL_DSDL
6 DATA_DSDL
L4
7 DIRGND
CL508
M4 WDCKR_DSDR
8 LRCLK_DSDR
CL509
AMUTE
9 AMUTE
R576 2.2k
N6
10 CTRLGND
RST_DAC CL510 FFC2
11 RESET
SDK_DAC CL511
12 MC
K10 SDO_DAC CL512
13 MDI
CL513
L11 CS_DAC
14 ZMS
R577 2.2k
L9
15 CTRLGND
CL514
M9
(Page 57)
16 DSD128_XDSD64
CL515
N10 DSD_XPCM
17 DSD_XPCM
CL516
N11 24M_OE
18 24M_OE
CL517
22M_OE
19 22M_OE
R578 2.2k
20 CLKGND
CL518
128FS_IN
21 FS128IN
R579 2.2k
22 CLKGND
CL519
23 FS512IN
J13
R549
24 CLKGND
100
K13 WDCKR_DSDR
R575
0
L12 R550 10 DSD_XPCM
L13 R551 100 WDCKL_DSDL
K11 R552 10 RST_DAC
K12 AMUTE
R553
10
R554
10
F10 SDI_DSP
R555 10
F11 SDO_DSP
R556 10
G9 SDK_DSP
G10 RST_DSP
R557
10
R558
10
C8 LRCLK_OUT_CIRRUS
R559 10
B8 BCLK_OUT_CIRRUS
R560 10
B13
R561 10
A13
D13
>135S
FPGA_INTERRUPT
C13 R562
10
FPGA DSP
(Page 60)
A8
A7
N2
M3
When these parts are damaged, exchange the complete mounted board.
>11S
DIGITAL IO
BOARD
CN4006
BOARD
(2/3)