Sony HAP-S1 Service Manual page 91

Pin No. Pin Name
N11 VDDARM23_CAP6
N12 VDD_CACHE_CAP
N13 VDDARM_CAP6
N14 VDDARM_IN6
N15 GND67
N16 VDDSOC_IN6
N17 VDDPU_CAP6
N18 GND68
N19 DI0_DISP_CLK
N20 DI0_PIN3
N21 DI0_PIN15
N22 EIM_BCLK
N23 EIM_DA14
N24 EIM_DA15
N25 DI0_PIN2
P1 CSI0_PIXCLK
P2 CSI0_DAT5
P3 CSI0_DATA_EN
P4 CSI0_MCLK
P5, P6 GPIO_19, GPIO_18
P7 NVCC_GPIO
P8 GND74
P9 VDDARM23_IN5
P10 GND70
P11 VDDARM23_CAP7
P12 GND71
P13 VDDARM_CAP7
P14 VDDARM_IN7
P15 GND72
P16 VDDSOC_IN7
P17 VDDPU_CAP7
P18 GND73
P19 NVCC_LCD
DISP0_DAT4,
DISP0_DAT3,
P20 to
DISP0_DAT1,
P24
DISP0_DAT2,
DISP0_DAT0
P25 DI0_PIN4
R1 GPIO_17
GPIO_16, GPIO_7,
R2 to R7 GPIO_5, GPIO_8,
GPIO_4, GPIO_3
R8 GND78
R9 VDDARM23_IN6
R10 VSSSOC_CAP1
R11 VDDARM23_CAP8
R12 GND75
R13 VDDARM_CAP8
R14 VDDARM_IN8
R15 GND76
R16 VDDSOC_IN8
R17 GND77
R18 NVCC_DRAM1
R19 NVCC_ENET
DISP0_DAT13,
R20 to
DISP0_DAT10,
R22
DISP0_DAT8
DISP0_DAT6,
R23 to
DISP0_DAT7,
R25
DISP0_DAT5
I/O
O Internal regulator output terminal
O Internal regulator output terminal (+1.1V)
O Internal regulator output terminal
- Power supply terminal for the cores regulator (+1.42V)
- Ground terminal
- Power supply terminal for the SOC and PU regulators (+1.42V)
O Internal regulator output terminal
- Ground terminal
O Clock signal output to the liquid crystal display
- Not used
O Data enable signal output to the liquid crystal display
- Not used
I Boot mode setting terminal
I Boot mode setting terminal
- Not used
I CONF_DONE signal input from the FPGA
- Not used
- Not used
O Reset signal output to the FPGA
- Not used
- Power supply terminal for the GPIO interface (+3.3V)
- Ground terminal
- Power supply terminal for the cores regulator
- Ground terminal
O Internal regulator output terminal
- Ground terminal
O Internal regulator output terminal
- Power supply terminal for the cores regulator (+1.42V)
- Ground terminal
- Power supply terminal for the SOC and PU regulators (+1.42V)
O Internal regulator output terminal
- Ground terminal
- Power supply terminal for the LCD interface (+3.3V)
O RGB signal (blue) output to the liquid crystal display
O Liquid crystal display backlight on/off control signal output terminal
O Reset signal output to the PCIe transceiver
- Not used
- Ground terminal
- Power supply terminal for the cores regulator
O Internal regulator output terminal (+1.1V)
O Internal regulator output terminal
- Ground terminal
O Internal regulator output terminal
- Power supply terminal for the cores regulator (+1.42V)
- Ground terminal
- Power supply terminal for the SOC and PU regulators (+1.42V)
- Ground terminal
- Power supply terminal for the DDR interface (+1.5V)
- Power supply terminal for the ENET interface (+3.3V)
O RGB signal (green) output to the liquid crystal display
O RGB signal (blue) output to the liquid crystal display
Description
Not used
Fixed at "L"
Fixed at "H"
"L": reset
Not used
Not used
"L": reset
Not used
Not used
HAP-S1
"H": backlight on
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