Sony HAP-S1 Service Manual page 96

HAP-S1
MAIN BOARD IC602 AR8035-AL1A (ETHERNET TRANSCEIVER, +1.1V/+1.8V REGULATOR)
Pin No. Pin Name
1 RSTN
2 LX
3 VDD33
4 XTALO
5 XTALI
6 AVDDL_6
7 RBIAS
8 VDDH_REG
9 TRXP0
10 TRXN0
11 AVDDL_11
12 TRXP1
13 TRXN1
14 AVDD33
15 TRXP2
16 TRXN2
17 AVDDL_17
18 TRXP3
19 TRXN3
20 INT
21 LED_ACT
22 LED_1000
23 CLK_25M
24 LED_10_100
25, 26 RXD3, RXD2
27 VDDIO_REG
28, 29 RXD1, RXD0
30 RX_DV
31 RX_CLK
32 TX_EN
33 GTX_CLK
34 to 37 TXD0 toTXD3
38 DVDDL
39 MDIO
40 MDC
96
I/O
I Reset signal input from the MPU
O Internal regulator output terminal (+1.1V)
- Power supply terminal (+3.3V)
O System clock output terminal (25 MHz)
I System clock input terminal (25 MHz)
- Power supply terminal (+1.1V)
O Bias current setting terminal
O Internal regulator output terminal (+2.5V)
I/O Two-way data (positive) bus with the LAN jack
I/O Two-way data (negative) bus with the LAN jack
- Power supply terminal (+1.1V)
I/O Two-way data (positive) bus with the LAN jack
I/O Two-way data (negative) bus with the LAN jack
- Power supply terminal (+3.3V)
I/O Two-way data (positive) bus with the LAN jack
I/O Two-way data (negative) bus with the LAN jack
- Power supply terminal (+1.1V)
I/O Two-way data (positive) bus with the LAN jack
I/O Two-way data (negative) bus with the LAN jack
O Interrupt signal output to the MPU
O LED drive signal output terminal
O LED drive signal output terminal
O 25 MHz clock signal output to the MPU
O LED drive signal output terminal
O RGMII receive data output to the MPU
O Internal regulator output terminal (+1.8V)
O RGMII receive data output to the MPU
O RGMII receive data valid signal output to the MPU
O RGMII receive clock signal output to the MPU
I RGMII transmit data enable signal input from the MPU
I RGMII transmit clock signal input from the MPU
I RGMII transmit data input from the MPU
- Power supply terminal (+1.1V)
I/O Two-way management data bus with the MPU
I Management data clock signal input from the MPU
Description
"L": reset
Not used
Not used
Not used