Sony HAP-S1 Service Manual page 101

FPGA DSP BOARD IC702 CS48L10-CNZR (AUDIO DSP)
Pin No. Pin Name
1 CLOCK
2 VPLL
3 GND_3
4 VD_4
5 VL_5
6 CLK/SCL
7 nCS
8 MISO/SDA
9 MOSI
nBUSY/HS0/
10
nEE_CS
11 nINT/HS1
12 nRESET
13 DBCK
14 VL_14
15 GND_15
16 VD_16
17 DBDA
18 MCLK
19 DAO_D1
20 DAO_LRCLK
21 DAO_SCLK
22 DAI_D1
23 DAI_LRCLK
24 DAI_SCLK
I/O
I 6 MHz clock signal input terminal
- Power supply terminal for the PLL (+1.2V)
- Ground terminal
- Power supply terminal for the digital core and memory (+1.2V)
- Power supply terminal for the digital interface (+3.3V)
I Serial data transfer clock signal input from the FPGA
I Chip select signal input from the FPGA
O Serial data output to the FPGA
I Serial data input from the FPGA
O Busy signal output to the FPGA
O Interrupt signal output to the FPGA
I Reset signal input from the FPGA
- Not used
- Power supply terminal for the digital interface (+3.3V)
- Ground terminal
- Power supply terminal for the digital core and memory (+1.2V)
- Not used
I Master clock signal input terminal
O Audio data output to the FPGA
I L/R sampling clock signal input from the FPGA
I Bit clock signal input from the FPGA
I Audio data input from the FPGA
I L/R sampling clock signal input from the FPGA
I Bit clock signal input from the FPGA
Description
"L": reset
Not used
HAP-S1
101