Block Diagram - Digital Audio Input Section - Sony HAP-S1 Service Manual

5-2.

BLOCK DIAGRAM - DIGITAL AUDIO INPUT Section -

DIGITAL AUDIO INTERFACE RECEIVER
OPTICAL
OPTICAL IN RECEIVER 63 RXIN1
IC4001
WAVE
J4023
SHAPER 58 RXIN6
COAXIAL IN
IC4002
31 XOUT
X4001
24.576MHz
32 XIN
39 38 37
27
HAP-S1
IC4004
DATA_DSDL
DATAOUT 16
BCLK-L
BCKOUT 14
LRCLK_DSDR
D4003
LRCKOUT 15
FREQUENCY MULTIPLIER
IC4008
MCKOUT 13 5 CLK_IN CLK_OUT 3
LOCK#
4
XMCK 30
36 40 25 35 23 24
D_ERROR
D_CKST
28 29 30 19 20 36 31 32 18
SYSTEM CONTROLLER
IC5006 (2/5)
DATA/CLOCK SELECTOR
IC4007
14 A3
Y3 12
13 B3
11 A2
Y2 9
10 B2
5 A1
Y1 7
6 B1
2 A0 CLOCK SELECTOR
Y0 4
3 B0 IC407
SELECT
2 B
1 Y 5
1 A
SELECT
6
CLOCK SELECTOR CLOCK SELECTOR
IC4006 IC410
1 A A 1
Y 5 5 Y
2 B B 2
COUNTER
SELECT SELECT
IC411
6 6
16
41 41
D/A CONVERTER
IC405
IOUTL+ 25 LINE AMP
5 DATA
IC402
IOUTL– 26
6 BCK
IOUTR+ 17 LINE AMP
IOUTR– 18 IC401
4 LRCK
7 SCL
MDI 11 D12
MC 12 E10
!MS! 10 D11
!RST! 14 K11
DATA_DSDL
L13
BCLK-L
N13
LRCLK_DSDR
K13
CLOCK
X400
BUFFER
22.5792MHz
IC408
SWITCHING
IC412
CLOCK
X401
BUFFER
24.576MHz
IC409
G13
L12
AMUTE
K12
SIGNAL PATH
HAP-S1
L L, R
>002B
MIX AMP
(Page 42)
IC400
R
FPGA
IC001 (2/2)
IO/DIFFIO_R2N
IO/DIFFIO_R4P/DM0R
IO/DIFFIO_R2P
IO/DIFFIO_R14P/DQ0R
IO/DIFFIO_R13N/DQ0R
IO/RUP3
IO/DIFFIO_R9P/DQ0R
CLK4/DIFFCLK_2N
IO/DIFFIO_R13P/DQ0R
IO/DIFFIO_R14N/DQ0R
AMUTE, D_ERROR, D_CKST
>003B
(Page 42)
: AUDIO (ANALOG)
: AUDIO (DIGITAL)
: AUDIO IN (DIGITAL)