Diagrams; Block Diagram - Hdd/Usb/Lan/Fpga/Dsp Section - Sony HAP-S1 Service Manual

HAP-S1
SECTION 5

DIAGRAMS

HAP-S1
5-1.

BLOCK DIAGRAM - HDD/USB/LAN/FPGA/DSP Section -

HDD1
HARD DISK DRIVE
HR+0 B14 SATA_RXP
HR–0 A14 SATA_RXM
HT+0 A12 SATA_TXP
HT–0 B12 SATA_TXM
CN4002
5V 1A
EXT
3
DP A6 USB_OTG_DP
2
DM B6 USB_OTG_DN
ANT1 WBC1
WLAN/BT
PATTERN ANTENNA
COMBO CARD
(L SIDE)
ANT2
DP E10 USB_H1_DP
PATTERN ANTENNA
(R SIDE)
DM F10 USB_H1_DN
CN4001
ETHERNET TRANSCEIVER
IC602 (1/2)
LAN (10/100/1000)
1
TRDP_0 9 TRXP0 RXD0 29 C24 RGMII_RD0
RXD1 28 B23 RGMII_RD1
2
TRDN_0 10 TRXN0 RXD2 26 B24 RGMII_RD2
RXD3 25 D23 RGMII_RD3
3
TRDP_1 12 TRXP1
TXD0 34 C22 RGMII_TD0
4
TRDN_1 13 TRXN1 TXD1 35 F20 RGMII_TD1
TXD2 36 E21 RGMII_TD2
5
TRDP_2 15 TRXP2 TXD3 37 A24 RGMII_TD3
6
TRDN_2 16 TRXN2 MDIO 39 V23 ENET_MDIO
MDC 40 V20 ENET_MDC
7
TRDP_3 18 TRXP3 RX_CLK 31 B25 RGMII_RXC
RX_DV 30 D22 RGMII_RX_CTL
8
TRDN_3 19 TRXN3 GTX_CLK 33 D21 RGMII_TXC
TX_EN 32 C23 RGMII_TX_CTL
4 XTALO CLK_25M 23 V22 ENET_REF_CLK
X601
INT 20 W22 ENET_RXD1
25MHz
5 XTALI RSTN 1 U21 ENET_CRS_DV
MPU
IC101 (1/3)
PICE_TXP B3 J2 GXB_RX0p
PICE_TXM A3 J1 GXB_RX0n
PICE_RXP B2 G2 GXB_TX0p
PICE_RXM B1 G1 GXB_TX0n
CLK1_P D7 J6 CLK12/DIFFCLK_7p/REFCLK0p
CLK1_N C7 J7 CLK13/DIFFCLK_7n/REFCLK0n
EIM_CS1 J23 A5 IO/DATA0
EIM_CS0 H24 A4 DCLK
EIM_D20 G20 D5 nCONFIG
CSI0_PIXCLK P1 J5 CONF_DONE
CSI0_DAT8 N6 M6 IO/DIFFIO_B3p/INIT_DONE
EIM_A25 H19 D13 IO/DIFFIO_T1BP/DQ0T
EIM_D23 D25 K6 nSTATUS
GPIO_17 R1 E6 CLK10/DIFFCLK_4n/REFCLK1n
RESET SWITCH
CSI0_MCLK P4 D10 IO/DIFFIO/R4n/DEV_CLRn
Q301
DATA SELECTOR SYSTEM CONTROLLER
IC5005 IC5006 (1/5)
0X 12 40 UART SYS/MPU
CSIO_DAT13 L1 13 X-COM
1X 14 72 PROG SYS/JIG
0Y 1 39 UART MPU/SYS
CSIO_DAT12 M2 3 Y-COM
1Y 5 73 PROG JIG/SYS
A
10
D5004
NANDF_CLE C15 47 MD0
XTALO B7
X401
24MHz
XTALI A7
RTC_XTALO C9
X403
32.768kHz
RTC_XTALI D9
40 40
FPGA AUDIO DSP
IC001 (1/2) IC702
IO/VREFB7N0 B10 22 DAI_D1
IO/DIFFCLK_T11N/DQ0T A11 24 DAI_SCLK
IO_B11 B11 23 DAI_LRCLK
CLK8/DIFFCLK_5N A9 19 DAO_D1
IO/DIFFCLK_T12N/DQ0T B8 21 DAO_SCLK
IO/DIFFCLK_T12P/DQ0T C8 20 DAO_LRCLK
IO/DIFFIO_R5P/DQ0R F10 8 MISO/SDA
IO/DIFFIO_R5N/DQ0R F11 9 MOSI
IO/DIFFIO_R6P/DQS0R/CQ0R/DPCLK8 G9 6 CLK/SCL
IO_F9 F9 7 nCS
CLK6/DIFFCLK_3N F13 10 nBUSY/HS0/nEE_CS
CLK7/DIFFCLK_3P F12 11 nINT/HS1
IO/DIFFIO_R6N/DEV_OE G10 12 nRESET
X201
CLK11/DIFFCLK_4p/REFCLK1p E7
50MHz
22M_OE
IO/DQS1R/CQ0R#/DPCLK7 H10
24M_OE
IO/VREFB5N0 H12
SIGNAL PATH
: AUDIO (DIGITAL)
: HDD
: USB
: LAN
: WIRELESS LAN
CLOCK
X701
CLOCK 1 BUFFER
6MHz
IC701
22M_OE, 24M_OE
>001B
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