Hpmc Caused By A Multi-Bit Memory Parity Error; Interpreting The Table - HP 743 Service Handbook

HPMC Caused by a Multi-Bit Memory Parity Error

An HPMC interruption is forced when a multi-bit memory parity error is detected during a
"DMA read" operation or fetching an I/D cache line (32 bytes).
Table 4-6 shows an example of the HPMC error information retrieved from Stable Storage
by the PIM command from the Interactive Testing Debug Environment.
Check Type
CPU State
Cache Check
TLB check
Bus Check
Assists Check
Assists State
System Responder Address
System Requester Address
System Controller Status

Interpreting the Table

The values in the Bus Check and System Responder Address words indicate that a multi-
bit memory parity error was detected by logic in the memory module. Ignore the value in
the System Controller Status word.
The System Responder contains the hexadecimal address of the faulty memory location.
Read the following section, Determining the Faulty Memory Card, to determine which
memory card contains the faulty memory location.
Dealing with HPMC (Uncorrectable Error)
Table 4-6 Multi-Bit Memory Parity Error
Word
Troubleshooting
Value
0x20000000
0x9e000004
0x00000000
0x00000000
0x00210004
0x00000000
0x00000000
0xnnnnnnnn
0x00000000
0x00000nnn
4-23