Figure 3-4 Blade Node Block Diagram Example - Silicon Graphics UV 2000 System User's Manual

3: System Overview
CPU/DDR3 Power
Vcore/
VSA
DDR3
DDR3
VPPL VTT
TOP NODE PCA
Clocks
Clocks
BMC to CMCEnet
POWER
CONN
BMC to CMCEnet
CPU/DDR3 Power
Vcore/
VSA
DDR3
DDR3
VPPL VTT
42
• The total memory within the NUMAlinked system is referred to as global memory.
A B
Chan-0
DDR3
A B
DDR3 Chan-1
A B
DDR3
Chan-2
A B
DDR3
Chan-3
PCIe Gen 3 X16
Spartan 6
PSOC
SGPIO
DDR3
SPI
BMC to CMCEnet
BMC to CMCEnet
A B
Chan-0
DDR3
A B
Chan-1
DDR3
A B
DDR3 Chan-2
A B
DDR3
Chan-3
BOTTOM NODE PCA W/BMC
Figure 3-4 Blade Node Block Diagram Example
P
R
O
C
1
QPI
C
O
N
PSOC
N
E
C
SGPIO
SGPIO
T
PSOC
O
R
FPGA
QPI
PCIe Gen 3 X16
BACKPLANE CONNECTOR
Local Bus 0 &1
HARP PCA
BNI Bus 0 & 1
HARP CONNECTOR
QPI
Only used
for BaseIO
PCIe X4
PCIe X4
Only used
for BaseIO
Used for:
PCIe x16 slot or
BaseIO card
(4) QFSP
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