Distributed Shared I/O; Chassis Management Controller (Cmc); Ccnuma Architecture; Cache Coherency - Silicon Graphics UV 2000 System User's Manual

Distributed Shared I/O

Chassis Management Controller (CMC)

ccNUMA Architecture

Cache Coherency

007-5832-002
Like DSM, I/O devices are distributed among the blade nodes within the IRUs. Each BaseIO riser
card equipped blade node is accessible by all compute nodes within the SSI (partition) through the
NUMAlink interconnect fabric.
Each IRU has a chassis management controller (CMC) located directly below the cooling fans in
the rear of the IRU. The chassis manager supports powering up and down of the compute blades
and environmental monitoring of all units within the IRU.
One GigE port from each compute blade connects to the CMC blade via the internal IRU
backplane. A second GigE port from each blade slot is also connected to the CMC. This
connection is used to support a BaseIO riser card. Only one BaseIO is supported in an SSI. The
BaseIO must be the first blade (lowest) in the SSI.
As the name implies, the cache-coherent non-uniform memory access (ccNUMA) architecture has
two parts, cache coherency and nonuniform memory access, which are discussed in the sections
that follow.
The SGI UV 2000 server series use caches to reduce memory latency. Although data exists in local
or remote memory, copies of the data can exist in various processor caches throughout the system.
Cache coherency keeps the cached copies consistent.
To keep the copies consistent, the ccNUMA architecture uses directory-based coherence protocol.
In directory-based coherence protocol, each block of memory (128 bytes) has an entry in a table
that is referred to as a directory. Like the blocks of memory that they represent, the directories are
distributed among the compute/memory blade nodes. A block of memory is also referred to as a
cache line.
Each directory entry indicates the state of the memory block that it represents. For example, when
the block is not cached, it is in an unowned state. When only one processor has a copy of the
System Features
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