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3.
The input bypass capacitors should be placed close to the VIN pins. Shortening
the traces of the SW node reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases switching voltage spikes
at these nodes.
4.
Some switching devices have exposed pad which should be soldered to a large
analog ground plane, as the analog ground copper acts as a heat sink. To
ensure proper adhesion to the ground plane, avoid using vias directly under the
device.
5.
For more detailed design information, please refer to the switching regulatorís
data sheet.
2.9
PCI Interface
1.
We highly recommend reserve terminations for ALL PCI signals. It is
much easier to remove terminations than adding them after the PCB has
been found to fail EMI.
2.
The trace length for all PCI signals must be limited to 7 inches.
3.
The trace length for PCI Clocks must be short for on-board PCI devices to mini-
mize the clock skew.
4.
The PCI clock traces should be parallel to their reference plane, usually ground
planes. That means the clock traces should be right beneath or on top of their
reference plane.
5.
There is NO board impedance specified in the PCI bus specification. We recom-
mend the trace impedance to be 60 Ω ± 10%, with a trace width/ spacing
design of 5 mil/10 mil.
6.
Add serial termination resistor and bypassing capacitor (tens of pF) to PCI clock
signals to match the trace impedance and enhance EMI.
EVA-X4300 System Design Guide
20
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