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20.
Recommended layout:
Trace length (include the substrate & PCB trace length) routing:
(a) The following signals of DDR2 SDRAM in each group must route near by in
the same plane:
Group (1): LDQS, /LDQS, LDQM, DQ [0...7]
Group (2): UDQS, /UDQS, UDQM, DQ [8...15]
Group (3): MA [0...13], BA [0...2], /RAS, /CAS, /WE, MCLK, /MCLK
i. The intra-signals trace length in each group better keeps the same, other-
wise keeps the mismatch less than 250 mils.
ii. The mismatch trace length between the inter-groups must be less than 400
mils.
(b) All signals avoid crossing over an unrelated plane or different power plane.
(c) Route traces with minimal layer transitions and minimize the total number of
turns & vias.
Signal
Data Strobe
Data Mask
Data Bus
Clock
Address
Command
VREF
Power/
GND
2.8
Switching Power
1.
Please check section 2.3 and DDR2 data sheet for the detailed power require-
ments of the DDR2 system.
2.
In a step-down switching regulator, the input bypass capacitor, the main power
switch and the freewheeling diode carry discontinuous currents with high dt/di.
For jitter-free operation, the size of the loop formed by these components should
be minimized.
Width/ Spacing/
Isolation
5 mil/ >20 mil/ 20 mil
5 mil/ >5 mil/ 15 mil
5 mil/ >5 mil/ 5 mil
5 mil/ >20 mil/ 20 mil
5 mil/ >5 mil/ 5 mil
Width > 20 mil
Maximum Length
2 inches
The mismatch of the dif-
ferential pair is ±10 mil
3 inches
Kept to a minimum
19
EVA-X4300 System Design Guide
Note
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