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Related Manuals for Advantech EVA-X4300
Summary of Contents for Advantech EVA-X4300
- Page 1 User Manual EVA-X4300 System Design Guide...
- Page 2 Copyright Advantech reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Advantech is believed to be accurate and reliable. However, Advantech does not assure any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
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Page 3: Table Of Contents
Chapter Layout Guide........3 BGA Layout Guideline................4 Package Outline..................6 Signal Arrangement .................. 8 EVA-X4300 Power Requirement............. 11 General Layout Rule ................11 Crystal / External Oscillator..............15 DDR2 Interface ..................16 Switching Power..................19 PCI Interface ................... 20 2.10 USB 2.0.................... - Page 4 EVA-X4300 System Design Guide...
- Page 5 Chapter Overview...
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Page 6: Chapter 1 Overview
Overview The EVA-X4300 is a fully static 32-bit x86-based processor that is compatible with a wide-range of PC peripherals, applications and operating systems, such as DOS, WinCE, Linux, and most popular 32-bit RTOSs (Real Time OS). It enables maximum software re-use based on its feature of legacy compatibility. The EVA-X4300 inte-... -
Page 7: Chapter 2 Layout Guide
Chapter Layout Guide... -
Page 8: Bga Layout Guideline
BGA Layout Guideline The package of EVA-X4300 is 581-ball PBGA. The ball diameter is 0.6 mm (24 mil); ball pitch is 1 mm (40 mil). There are 6 rows of balls arranged along the edge of the package. For 6-layer: Ball pad diameter: 24 mil Traces width/ spacing for Signals: 5.5/ 5 mil... - Page 9 Via-to-pad spacing (center to center): 30 mil Note! All the Vias must be covered by solder mask. To minimize inductance, power vias should be as large as possible and take good care of the inadvertently cut of the ground and power planes. EVA-X4300 System Design Guide...
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Page 10: Package Outline
Package Outline EVA-X4300 System Design Guide... - Page 11 EVA-X4300 System Design Guide...
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Page 12: Signal Arrangement
○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ A B C D E F G H L M N P R T U V W Y AA AB AC AD AE AF Pin #1 Corner EVA-X4300 System Design Guide... - Page 13 SDD14 RTS3_/ AFD_/ SLIN_/ TEST5 TEST6 SIN3 TESTCLK PD3/SDD3 PDD9 SRST_ SDD15 SDD12 CTS3_/ DCD3_/ TEST7 TEST8 SOUT3 PD0/SDD0 PD1/SDD1 PD2/SDD2 PINT SIOR_ SDRQ DTR3_/ RI3/ DSR3_/ INIT_/ STB_/ PRST_ PDD3 SDACK_ SIORDY SCBLID_ SDD13 SCS0_ EVA-X4300 System Design Guide...
- Page 14 DRQ1 BALE IRQ15 PIORDY PIOW_ PDD0 PDD8 Vdd_io Vdd_io DACK_3 SA16 DACK_1 SA11 IOCS16_ IRQ11 PCS0_ PDD4 PDD15 PDD14 IOW_ SA12 SA14 SA13 IRQ3 IRQ14 RSET_DR MEMCS16 PDD13 PDRQ PDACK_ PCBLID_ PIOR_ PCS1_ SA15 IRQ6 IRQ4 EVA-X4300 System Design Guide...
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Page 15: Eva-X4300 Power Requirement
The propagation speed on typical PCB is about 170 pS/inch (50 Stripline), Ω 150pS/inch (50 Microstrip). Ω There are 4 properties affect the performance of the transmission line: Impedance: reflection/ distortion Time delay High-Frequency Loss: limit signal bandwidth and transmission distance Crosstalk: coupling EVA-X4300 System Design Guide... - Page 16 RF return current path. Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is connected to the ground plane through stitches of vias. Example for BGA Power/ Ground routing: EVA-X4300 System Design Guide...
- Page 17 A clean or quiet ground must be located at the point where interconnects leave the system. Connect (“Bridge”) those grounds with only one connection. Only those signals required for operation or interconnect can run into the isolated area. EVA-X4300 System Design Guide...
- Page 18 Supply (V) Note DDR2 For detail of power-on-straps function, please refer to the EVA-X4300 data sheet. Do follow the power-on sequence to prevent excessive current from the power supplies during power-up and power-down periods: Power-up core supply (VDD_CORE), and then power-up the I/O supply (DVDD).
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Page 19: Crystal / External Oscillator
The other way is to use an external 14.318MHz oscillator, and directly route the oscil- lator is output into XTALi pin of EVA-X4300. A serial damping resistor and a bypass capacitor are recommended for EMI reduction. The XTALo pin should leave uncon- nected. -
Page 20: Ddr2 Interface
DDR2 Interface It is assumed that the reader is familiar with the specification and the basic elec- trical operation of the DDR2 interface. EVA-X4300 DDR2 interface substrate conductors’ length for signal integrality: EVA-X4300 Substrate Conductor Length Net Name Length in microns MA[0] 13283.31... - Page 21 The purpose is to provide a path for return currents to minimize crosstalk and EMI. The DDR2 devices should be placed as close to EVA-X4300 as possible. The distance between DDR2 devices and EVA-X4300 should less than 3 inches. Other devices should be kept away to ensure other signals do not interfere with the DDR2 interface.
- Page 22 Impedance (Ω) Value (Ω) Note Clock± Near EVA-X4300 Differential, 90 DQS± Near DDR2 A[0..13], BA[0..2], Controls Near EVA-X4300 DQ[0..15] Near DDR2 MD[0..15] Near EVA-X4300 Note! Termination value may have to be adjusted according to manufacturing condition. EVA-X4300 System Design Guide...
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Page 23: Switching Power
In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry discontinuous currents with high dt/di. For jitter-free operation, the size of the loop formed by these components should be minimized. EVA-X4300 System Design Guide... -
Page 24: Pci Interface
60 Ω ± 10%, with a trace width/ spacing design of 5 mil/10 mil. Add serial termination resistor and bypassing capacitor (tens of pF) to PCI clock signals to match the trace impedance and enhance EMI. EVA-X4300 System Design Guide... -
Page 25: Usb 2.0
8 mil/ 8 mil/ >20 mil. And the mismatch of the differential pairs should be less than ±70 mil. These values may vary depending on the actual PCB parameters. The maximum trace length of USB differential pairs should be less than 2”. EVA-X4300 System Design Guide... - Page 26 USB data lines must be routed as “critical signals”. Locate the USB connector close to EVA-X4300. The DP and DM signals in a pair must be routed in parallel to each other. Do not route these traces near high frequency signals. Guard ground traces on each side of the signal pair can minimize the induced common mode noise.
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Page 27: Ide
1 KΩ. All IDE signals need to be serial terminated. Place the termination resistors for A[0...2], CS[0..1], /IOR, /IOW and /DACK near EVA-X4300. Place the termina- tion resistors for D[0..15], DRQ, IORDY, and IRQ near IDE connector. The termination value should be optimized to compensate for transceiver and trace impedance to match the characteristic cable impedance. -
Page 28: Lpc Interface
2.12 LPC Interface A Low Pin Count (LPC) controller is integrated in EVA-X4300. The LPC interface is to replace ISA interface serving as a bus interface between the system processor and peripherals (e.g. LPC super I/O chip). Many of the signals are the same as signals found on the PCI interface. -
Page 29: 10/100 Lan
Magnetics Selection Guide: Manufacturer Part Number Note Mingtek HN16005CG Keep the distance between the EVA-X4300 and the RJ-45 connector short (under 4”). Route the differential traces, TX±, RX±, TD± & RD±, for 100 Ω differential impedance. EVA-X4300 System Design Guide... - Page 30 “Bridge” or Ferrite Bead. Please refer to section 2.4 for more details. Place the external resistor of ISET, pin J24, as close to the EVA-X4300 as possible. And connect another end of the external resistor to the isolated analog ground plane described above.
- Page 31 Avoid over-damping which affects LAN stability. It is recommend to place 51 ohm and 22 pF from PCI AD0~AD3. EVA-X4300 System Design Guide...
- Page 32 EVA-X4300 System Design Guide...
- Page 33 Appendix References...
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Page 34: Appendix A References
“EMC and the Printed Circuit Board”, Mark I. Montrose “High-speed Digital Design”, Howard W. Johnson, PH.D. “Noise reduction Techniques in the Electronic System”, Henry W. Ott “Printed Circuit Board design Techniques for EMC Compliance”, Mark I. Mon- trose. EVA-X4300 System Design Guide... - Page 35 EVA-X4300 System Design Guide...
- Page 36 No part of this publication may be reproduced in any form or by any means, electronic, photocopying, recording or otherwise, without prior written permis- sion of the publisher. All brand and product names are trademarks or registered trademarks of their respective companies. © Advantech Co., Ltd. 2008...