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18.
Ensure that any signal passing between those sections runs ONLY through the
"bridge", and run the signals on a layer adjacent to the bridge to maintain RF
return path.
19.
If analog or digital power is not required in the isolated area, the unused power
plane can be redefined as a second ground plane, referenced to the main
ground plane by stitches of vias within the isolated area.
20.
Connect system Power-on and H/W Reset to "Power-good" input of EVA-
X4300, then use "/PCI_RST" output of EVA-X4300 to reset ALL peripherals.
21.
The power-on-strap pins are combined with the memory address bus, which
belong to DRAM power category. So the pull-high resistors should connect to
the same supply (VCCO) of DRAM interface. That is:
DRAM type
SDR
DDR2
For detail of power-on-straps function, please refer to the EVA-X4300 data sheet.
22.
Do follow the power-on sequence to prevent excessive current from the power
supplies during power-up and power-down periods:
Power-up core supply (VDD_CORE), and then power-up the I/O supply
!
(DVDD).
!
Power-down I/O supply (DVDD), and then power-down the core supply
(VDD_CORE).
23.
Recommend Termination:
Signal
Clocks 24M
PCI clock
PCI signal
DDR Clocks
DDR signal
24.
Recommended PCB stack up:
a. 4 layers
Layer
1
2
3
4
EVA-X4300 System Design Guide
Zs (Ω)
Termination(Ω)
26
7.2
13.2
19
19
Type
Description
Signal
Top Routing
FR4/ 5mil
Plane
Ground
FR4/ 40mil
Plane
Power
FR4/ 5mil
Signal
Bottom Routing
Supply (V)
3.3
1.8
Trace impedance (Ω)
22
22
51
33
33
Material/ Thickness
Copper/ 0.5~1oz
Copper/ 1oz
Copper/ 1oz
Copper/ 0.5~1oz
14
Note
60
60
60
90, Differential
60
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