Programmable Step Attenuator; Synthesizer Circuits; Reference/Control Board Circuits - Aeroflex NAV 2000R Operation Manual

4.6 PROGRAMMABLE STEP ATTENUATOR

The Programmable Step Attenuator provides control over the RF output power level. The output can be
switched from 0 dBm to -127 dBm in 0.1 dB steps. It is driven by the Programmable Step Attenuator
Control circuitry on the Audio Board.

4.7 SYNTHESIZER CIRCUITS

The synthesizer generates a CW frequency at a -20 dBm level in 10 Hz steps from 150 kHz to 450 MHz.
To set the synthesizer frequency, the NAV 2000R CPU board first checks the new frequency flag (RAM
location 5 of REF/CONTROL board within the synthesizer) to verify that the last frequency loaded has
been processed. The new frequency is loaded as a BCD value (LSB=10 Hz) in RAM locations 0 through
3. The new frequency flag is then set. The synthesizer microprocessor, upon seeing the new frequency
flag set, reads the new frequency value and converts it into the proper control signal required by the
synthesizer circuitry.
Circuits of the synthesizer reside on the REFERENCE/CONTROL board, the RF/OUTPUT board, the
MAIN VCO, and the 400 MHz VCO. The REF/CONTROL board generates the frequency standards and
the control signals required for selection of NAV 2000R RF frequencies.
contains the phase lock loop circuitry, dividers, filters and leveling loop circuits required to produce these
frequencies. The MAIN VCO covers a frequency range of 225 MHz to 456.25 MHz. The 400 MHz VCO
generates a 400 MHz signal when phase locked to the reference. Each board will be covered separately
in the following discussion.

4.7.1 REFERENCE/CONTROL BOARD CIRCUITS

For the following discussion, refer to the JPN Drawing 02-5852-00 in Section V. Control of the
synthesizer is maintained by microprocessor U1. Communication with the NAV2000R main CPU is
accomplished by means of RAM U2. This memory may be read or written either by the board
microprocessor U1, or by means of the NAV 2000R system buss. This access is time multiplexed. The
system buss addressed this memory by placing an address of between 0800h and 1000h on its address
buss and pulling the Synthesizer BUS REQUEST line low. Decoder U30 detects this combination and
the lack of read or write cycles of the on board processor and outputs a low on pin 14 of U30. This
connects RAM U2 address and data bus to the system bus by means of ICs U3, U4, and U29. Inverted
by U12, a low on U30-14 produces a high on the J, K not, and CLR not inputs of flip flop U11. The ALE
(address latch enable) clocks this flip flop synchronizing the internal bus with the system bus. Seeing
BUS GRANT low, the system bus completes its transition. Microprocessor U1
taking P1.0 (U1-1) low. With P1.0 low, either RD not or WR not will enable the outputs of latch U10 and
buffer U5. Thus, a read or write is generated to the RAM address selected.
To load a frequency, the microprocessor first outputs data serially to the MAIN PLL located on the
RF/OUTPUT board. This is done using three lines, PLL CLK (P2.0), PLL DATA (P2.2), and PLL EN not
(P2.2). The values loaded represents the divide ratios required by the main phase lock loop. Then the
microprocessor outputs nine discrete controls. Eight are outputted via the microprocessor bus and
latched by U6. One is directly controlled using P2.3 of the microprocessors I/O. The eight latched control
signals select the proper filter, RF divider, and VCO(s). The last discrete control signal allows stable
VCO operation whenever a change in VCO selection is required. Finally, the microprocessor loads the
Direct Digital Frequency Synthesizer with values required to produce the proper MAIN PLL reference.
The value loaded here is the phase increment required to produce a 700 kHz signal plus or minus (+/-)
1.2 kHz (as required) from the 10 MHz clock.
NAV 2000R SIGNAL GENERATOR - REV. 0 – JULY 26, 2007 - PG 4-24
Aeroflex Operation Manual
The RF/OUTPUT board
selects RAM U2 by