Dsp Board Circuit Description - Aeroflex NAV 2000R Operation Manual

Aeroflex Operation Manual
All board timing is derived from the processor clock. Crystal Y1, and capacitors C1 and C2 set the clock
frequency to 16.384 MHz. Inverter U9 buffers the processor oscillator to drive all Mother board circuits
requiring a clock.
The CPU board interfaces with the keyboard by means of seven lines. These consist of six key value
lines KD0-5 and a key is pressed indicator KEYIN. KD0-4 lines are latched within the keyboard assembly
while KD5 representing a bank select is latched on the CPU board by U38, clocked by KEYIN. KEYIN is
applied to U28. U28 will generate a interrupt request to processor U1 whenever KEYIN goes high. The
interrupted processor then reads the key value through tri-state buffer U39. KEYIN inverted by U16 is
also applied to U28. A low at pin 34 of U28 starts a timer within U28. If a key is held for longer then the
programmed times additional interrupts will occur.
Processor U1 determines and drives the NAV 2000R display. Timers within U1 generate the horizontal
sync and vertical sync for the display. The values and fields displayed are generated by software within
the processor and written to video rams U33 and U34. Interface to the processor bus is accomplished by
ICs U30, U31, and U32. The video rams are dynamic, and need RAS and CAS timing for data writes and
reads. Programmable logic IC U30 generates this timing. Quad 2 to 1 decoders U31 and U32 converts
the 16 bit processor address into the two 8 bit row and column address. The video ram has two ports,
the one discussed above and serial ports. Programmable logic within U35 generates the video ram
output timing. Demultiplexer U36 converts the 8 serial ports of the two video rams into a single serial
video data output. Hex D flip/flop U37 synchronizes the Video data, vertical and horizontal syncs to the
display clock.
Information is passed between the CPU board and other circuitry by means of a parallel bi-directional
bus. This bus consists of eight data lines which are multiplexed with the eight lower address lines, five
additional address lines, address latch enable, a direction line, read and write, four request lines, and a
bus granted line. The CPU board controls all bus transactions. When the CPU board needs to send or
receive a byte of information to or from one of the other cards, it pulls the bus request line going to the
card of interest low. IC U7 selects one of the four cards based on processor's (U1) address lines A13 and
A14. The card addressed replies by pulling BUS GRANTED low. BUS GRANTED is common to all
cards. This wired OR pull down is pulled to +5 v only through pull up resistor R9 on the CPU card. Once
a bus request is asserted, processor U1's bus cycle will not complete until either BUS GRANTED is
returned or a time out circuit on the CPU board expires. As can be seen on the CPU board schematic,
inverted BUS GRANTED is ORed with monostable multivibrator (U15) output and applied to the ready pin
of processor U1. Monostable multivibrator (U15) is retriggerable. A delay in the return of BUS
GRANTED extends the read or write signals allowing the board addressed to set its own bus speed. The
timeout furnished by monostable multivibrator (U15) is nominally 5 microseconds. Therefore, a wide
range of board interfaces may be handled. Tri-state buffers U20 and U21 outputs are turned on only
during bus requests isolating the processor bus from the external bus except during external bus
transactions. Bi-directional bus transceiver U19 is similarly controlled, with the external bus isolated
except during external bus operation.

4.5.3 DSP BOARD CIRCUIT DESCRIPTION

The DSP board consists of a digital signal processor (U1), a digital filter (U7), a D/A converter (U15), a
lowpass filter (1/2 U17), a buffer amplifier (1/4 U17), and interface logic (U8, U9, U10) to talk to the CPU
board through connector J1 (see Aeroflex schematic 02-5743-10 for DSP board circuit diagram).
The DSP processor runs at 10.199 MHz. This is obtained by dividing the clock of the digital filter U7 by 2.
The DSP generates a 2.5 MHz serial clock (SCLK1) for the bit clock input (BCI) of the digital filter. The
DSP also outputs a 79.68 KHz transmit/receive frame sync pulse. This is divided by U5 to obtain 39.84
KHz. This is applied to the SDSY input of the filter which controls the serial data word rate.
NAV 2000R SIGNAL GENERATOR - REV. 0 – JULY 26, 2007 - PG 4-15