Rf Modulator Module Circuit Description; Rf Modulator Module Block Diagram; Rf Modulator Module Bus Interface Circuitry - Aeroflex NAV 2000R Operation Manual

A crystal between XI input and XO output of the digital filter and a capacitor from XO to ground produces
the digital filter's 20.398 MHz clock frequency. This frequency is divided and used to clock the DSP
processor. The bit clock input (BCI) is 2.5 MHz, which is 64 times the sampling frequency of 39.84 KHz.
The 8 times oversampling filter causes the image frequency to occur between 8Fs +/- Fs/2, where Fs is
the sampling frequency.
oversampling frequency of 320 KHz. A 3 pole analog filter is used following the D/A converter, to remove
unwanted signal outside the desired band of 0 to 18 KHz.
would occur between Fs +/- Fs/2, which are between 20 KHz and 60 KHz. This would require a higher
order lowpass filter with a steep roll off between 18 KHz and 20 KHz.
The Bit Clock Output (BCO) of the digital filter is applied to the Clock Input (CLK) of D/A converter U15.
The Word Clock Output (WCO) of the filter is connected to the latch enable (LE) pin of the D/A. The Left
Channel Data output (DLO) is applied to the serial data input of the D/A converter.
The output of the D/A converter passes through a RC filter consisting of R5 and C1. Following this is a
two pole low pass filter consisting of two sections of a quad operational amplifier, U17. The filtered output
is available for use by the audio board at pin 14 of connector J1. A buffer, consisting of a section of U17
and associated discrete components, provides the output at the BNC connector J5. The amplitude of this
output is adjustable by the potentiometer R9.
The DSP processor uses two 8 bit ROMS, U11 and U12 to read the 16 bit sine lookup table. U13 is an 8-
bit RAM used as a boot ROM on power up and data memory RAM after booting is completed. The 14 bit
DSP address bus is buffered by U9 and U10 and sent to connector J1 to be shared by the CPU board.
The middle 8 bits of the DSP data bus is buffered by U8 and connected to J1 to allow CPU board access
to the data bus. The CPU board's multiplexed address and data busses are connected to both U8 and
U9. The bus request input (BR) and the bus grant output (BG) of the DSP processor are ORed, inverted
and applied to the J input of U6. The Q output of U6 is in sync with the DSP clock. This is applied to the
base of Q1. The R-C combination of R4 and C68 speeds up the switching time of Q1. The output at the
collector of Q1 is used by the CPU board as a bus grant signal.

4.5.4 RF MODULATOR MODULE CIRCUIT DESCRIPTION

This section contains an operational description of the RF Modulator Module Circuitry. The Audio Board,
RF Modulator Board and Variable Attentuator are each covered separately.

4.5.5 RF MODULATOR MODULE BLOCK DIAGRAM

JPN Drawing 40-9520-51, located in Section V, shows a block diagram of the RF Modulator Module. The
current discussion on the operation of the Audio Board covers the Audio Board features shown on the
block diagram. Also refer to the Audio Board schematic JPN Drawing 02-5761-20.
4.5.6 RF MODULATOR MODULE BUS INTERFACE CIRCUITRY (AUDIO BD-A1)
The RF Modulator Module interfaces to the NAV 2000R via system bus connector, J1. RN1 and RN2
provide pull ups to the system data bus, address bus, and control lines. The bus request is the system
bus request 1. The features of the module can be addressed using system bus address lines A8 through
A11. MOD AUDIO 1 is an internal audio input, which is supplied from the system DSP Board. U1 is a
bus transceiver, which controls the direction of the data on the bus and also provides bus driving
capabilities. U3 is a 3 to 8 line decoder, which selects the RF Modulator Module component to be
accessed. A description of the functions addressed using the decoder is listed below as well as bus
request / bus grant circuitry.
NAV 2000R SIGNAL GENERATOR - REV. 0 – JULY 26, 2007 - PG 4-16
Aeroflex Operation Manual
The image frequency occurs between 300 KHz and 340 KHz due to the
Without a digital filter, the image frequency