Rf/Output Board Circuits - Aeroflex NAV 2000R Operation Manual

Aeroflex Operation Manual
The Direct Digital Frequency Synthesizer is composed of the DDFS integrated circuit U15, Digital to
Analog Converter U16, and low pass filter C13,L1,C14, and L2. The DDFS contains a 32 bit phase
accumulator and a phase to sinewave value converter. For each 10 MHz clock cycle, the DDFS IC adds
the phase value loaded by the Microprocessor to the previous phase value and outputs the sine value of
this new phase to the DAC. The DAC converts this sine value to a amplitude of current. Resistor R12
develops a corresponding voltage. The full scale current is set by resistor R11 and reference voltage
source U17. This sampled signal, produced by the DAC, is filtered by the low pass filter to remove the
sampling frequency.
The output of the DAC is applied to the gate of transistor Q2. Applied to the source of Q2 is a 10 MHz
square wave. This square wave causes Q2 to switch on and off to generate a mixing function, multiplying
the 10 MHz and 700kHz. The drain of Q2 is tuned to 10.7 MHz and matches this output to the crystal
filter FL1. FL1 is a four pole filter compassed of two cans and coupling capacitor C18. The output of this
filter is matched to the input of amplifier transistor Q2 by means of transformer T2. The output of Q2 is
matched to 50 ohms by transformer T3. The 10.7 MHz produced is used as the reference frequency for
the MAIN PLL on the RF/OUTPUT board.
The synthesizer frequency standard is the Temperature Compensated Voltage Controlled crystal
Oscillator (TCVCXO) Y1. The output of this TCVCXO is a 5 volt 10 MHz square wave. The voltage
control pin (pin 4) is biased at 2.5 Vdc internally, which corresponds to its center frequency. In operation
without an external frequency standard, this input is disconnected by means of analog switch U25. But,
when an external standard is connected, this input is controlled within a phase lock loop. Applying a 10
MHz standard at INPUT J6 causes comparator U20 to operate. Seeing this signal, inverter U21 charges
C35 through diode CR1. When the voltage on C35 exceeds the threshold voltage of U21 pin 5, the output
at U21 pin 6 goes low. The output of comparator U20 is gated to phase comparator U23 and the voltage
control pin of TCVCXO Y1 is connected to the output of the loop filter present at Op Amp output U24 pin
1 through analog switch U25. The internal standard is then pulled into phase lock with the external
standard, thus moving the reference frequency to that of the external standard. The output of TCVCXO
Y1 is buffered by CMOS gates of U22 and U21, and used as clocks for the microprocessor and DDFS,
used to drive the 10.7 mixer, and sent to the 10 MHz OUTPUT J7 through transformer T7.

4.7.2 RF/OUTPUT BOARD CIRCUITS

Refer to the JPN schematic 02-5868-00 during the following discussion. The RF/OUTPUT board
consists of a MAIN PLL, RF frequency dividers, harmonic suppression filters, a 400 MHz PLL, a Mixer
and filter, and output leveling.
NAV 2000R SIGNAL GENERATOR - REV. 0 – JULY 26, 2007 - PG 4-25