Nexcom PEAK650VL2B User Manual page 30

Peak 650 User's Guide
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle.
The Choice: 5/7, 7/9.
SDRAM RAS-to-CAS Delay
This field let you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is
written to, read from, or refreshed.
performance. This field applies only when synchronous DRAM is installed in the system.
The Choice: 2, 3.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM refresh,
the refresh may be incomplete and the DRAM may fail to retain data. Fast gives faster performance; and
Slow gives more stable performance.
system.
The Choice: 2, 3.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better system
performance. However, if any program writes to this memory area, a system error may result.
The choice: Enabled, Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
any program writes to this memory area, a system error may result.
The Choice: Enabled, Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
be cached. The user information of peripherals that need to use this area of system memory usually
discusses their memory requirements.
The Choice: Enabled, Disabled.
CPU Latency Timer
When enabled this item, the CPU cycle will only be deferred after it has been held in a
clocks and another ADS# has arrived. When disabled, the CPU cycle will be deferred immediately after
the GMCH receives another ADS#.
The Choice: Enabled, Disabled.
BIOS Setup
Fast gives faster performance; and Slow gives more stable
This field applies only when synchronous DRAM is installed in the
Rev. A October 2000
When this area is reserved, it cannot
noop Stall  for 31
However, if
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