Table 59: Memory Ras Configuration Status Sensor - Event Trigger Offset - Next Steps - Intel S1400FP Manual

System Event Log Troubleshooting Guide for EPSD Platforms Based on Intel
Event Trigger Offset
Hex Description
01h RAS configuration
enabled.
00h RAS configuration
disabled.
Revision 1.1
Byte Field
13 Event Direction and [7] Event direction
Event Type
[6:0] Event Type = 09h (digital Discrete)
[7:6] – 10b = OEM code in Event Data 2
14 Event Data 1
[5:4] – 10b = OEM code in Event Data 3
[3:0] – Event Trigger Offset as described in Table 59
15 Event Data 2 RAS Configuration Error Type
[7:4] = Reserved
[3:0] = Configuration Error
16 Event Data 3 RAS Mode Configured
[7:4] = Reserved
[3:0] = RAS Mode
Table 59: Memory RAS Configuration Status Sensor – Event Trigger Offset – Next Steps
Description
User enabled mirrored channel mode
in setup.
Mirrored channel mode is disabled
(either in setup or due to unavailability
of memory at post, in which case post
error 8500 is also logged).
Intel order number G90620-002
Xeon Processor E5 4600/2600/2400/1600/1400 Product Families
® ®
Description
0b = Assertion Event
1b = Deassertion Event
0 = None
3 = Invalid DIMM Configuration for RAS Mode
All other values are reserved.
0h = None (Independent Channel Mode)
1h = Mirroring Mode
2h = Lockstep Mode
4h = Rank Sparing Mode
Informational event only.
1. If this event is accompanied by a post error 8500, there was a problem
applying the mirroring configuration to the memory. Check for other errors
related to the memory and troubleshoot accordingly.
2. If there is no post error, mirror mode was simply disabled in BIOS setup and
this should be considered informational only.
Memory Subsystem
Next Steps
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