Table 62. Processor Status Sensor Implementation - Intel S2600KPFR Product Specifications

S2600kp series

page of 205

/ 205
Contents
Table of Contents
Bookmarks

Table of Contents

Platform Management

1. A Rearm Sensor Events command is executed for the processor status sensor.

2. An AC or DC power cycle, system reset, or system boot occurs.

The BMC provides system status indication to the front panel LEDs for processor fault

conditions shown in Table 60.

CPU Presence status is not saved across AC power cycles and therefore will not generate a de-

assertion after cycling AC power.

Offset

Internal error (IERR)

Thermal trip

FRB1/BIST failure

FRB2/Hang in POST failure

FRB3/Processor startup/initialization failure (CPU fails to start)

Configuration error (for DMI)

SM BIOS uncorrectable CPU-complex error

Processor presence detected

Processor disabled

Terminator presence detected

Note:

Fault is not reflected in the processor status sensor.

9.3.11.2 Processor Population Fault (CPU Missing) Sensor

The BMC supports a Processor Population Fault sensor. This is used to monitor for the

condition in which processor slots are not populated as required by the platform hardware to

allow power-on of the system.

At BMC startup, the BMC will check for the fault condition and set the sensor state accordingly.

The BMC also checks for this fault condition at each attempt to DC power-on the system. At

each DC power-on attempt, a beep code is generated if this fault is detected.

The following steps are used to correct the fault condition and clear the sensor state:

1. AC power down the server.

2. Install the missing processor into the correct slot.

3. AC power on the server.

9.3.11.3 ERR2 Timeout Monitoring

The BMC supports an ERR2 Timeout Sensor (1 per CPU) that asserts if a CPU's ERR2 signal has

been asserted for longer than a fixed time period (> 90 seconds). ERR2 is a processor signal

that indicates when the IIO (Integrated IO module in the processor) has a fatal error which

could not be communicated to the core to trigger SMI. ERR2 events are fatal error conditions,

112