Memory Address Parity Error; Table 65: Address Parity Error Sensor Typical Characteristics - Intel S1400FP Manual

Memory Subsystem
System Event Log Troubleshooting Guide for EPSD Platforms Based on Intel
Event Trigger Offset
Hex Description
7.5.2

Memory Address Parity Error

Address Parity errors are errors detected in the memory addressing hardware. Because these affect the addressing of memory
contents, they can potentially lead to the same sort of failures as ECC errors. They are logged as a distinct type of error because
they affect memory addressing rather than memory contents, but otherwise they are treated exactly the same as Uncorrectable ECC
Errors. Address Parity errors are logged to the BMC SEL, with Event Data to identify the failing address by channel and DIMM to the
extent that it is possible to do so.
Byte Field
8 Generator ID 0033h = BIOS SMI Handler
9
11 Sensor Type 0ch = Memory
12 Sensor Number 13h
13 Event Direction and [7] Event direction
Event Type
[6:0] Event Type = 6Fh (Sensor Specific)
[7:6] – 10b = OEM code in Event Data 2
14 Event Data 1
[5:4] – 10b = OEM code in Event Data 3
[3:0] – Event Trigger Offset = 2h
[7:5] – Reserved. Set to 0.
15 Event Data 2
[4] – Channel Information Validity Check:
[3] – DIMM Information Validity Check:
78
Description

Table 65: Address Parity Error Sensor Typical Characteristics

0b = Assertion Event
1b = Deassertion Event
0b = Channel Number in Event Data 3 Bits[4:3] is not valid
1b = Channel Number in Event Data 3 Bits[4:3] is valid
0b = DIMM Slot ID in Event Data 3 Bits[2:0] is not valid
Intel order number G90620-002
Xeon Processor E5 4600/2600/2400/1600/1400 Product Families
® ®
Next Steps
5. Consider replacing the DIMM as a preventative measure.
For multiple occurrences, replace the DIMM.
Description
Revision 1.1