MATSONIC MS7177C User Manual page 60

PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support de-
lay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
PCI#2 Access #1 Retry
When set to Enabled, the AGP Bus (PCI#2) access to PCI Bus (PCI#1)
is executed with the error retry feature.
AGP Master 1 WS Write
This implements a single delay when writing to the AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By de-
fault, two-wait states are used by the system, allowing for greater
stability.
Memory Parity/ECC Check
Enable this item to allow BIOS to perform a parity check to the POST
memory tests. Select Enabled only if the system DRAM supports parity
checking.
Default: Enabled
Default: Enabled
Default: Disabled
Default: Disabled
Default: Disabled
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