Toshiba Tecra M2V Maintenance Manual page 23

1.2 System Unit Block Diagram
The system unit is composed of the following major components:
Processor
®
• Intel
Pentium
– Processor core speed:1.40GHz/1.50GHz/1.60GHz/1.70GHz
– Processor bus speed: 400MHz
– Integrated L1 cache memory: 32KB instruction cache and 32KB write-back
data cache, 4-way set associative
– Integrated L2 cache memory: 1MB ECC protected cache data array, 8-way set
associative
– Integrated NDP
Memory
Two BTO-compatible memory slots are provided. Expansion up to 2GB (2,048MB) is
available.
• DDR-SDRAM (Double Data Rate - Synchronous DRAM)
• 128MB/256MB/512MB/1GB selectable
– 128 MB (16M×16bit×4)
– 256 MB (16M×16bit×8)
– 512 MB (32M×8bit×16)
– 1GB
• 200 pin, SO Dual In-line Memory Modules (SO-DIMM)
• 2.5 volt operation
• Supports DDR266 (128MB, 256MB, 512MB and 1GB) and DDR333 (256MB,
512MB and 1GB)
• Supports PC2100 and PC2700
Intel MontaraGM+ (North Bridge)
• One Intel 855GM (GMCH-M) is used.
• Features:
®
− Intel
Pentium
− DRAM control (supports DDR266/DDR333)
− Built-in graphic control
− RGB, DVO interface
− AGP master slave interface (complies with AGP V2.0)
− Supports Intel Speed step Technology
− 732-ball (37.5x37.5mm) micro FCBGA package
TECRA M2V Maintenance Manual (960-476)
®
M Processor 1.40GHz/1.50GHz/1.60GHz/1.70GHz
(64M×8bit×16)
®
M Processor System bus support
1 Hardware Overview
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