Intel Itanium Processor 9500 Series Errata; November - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Specification

®
Table 6. Intel Itanium
Processor PAL
Stepping Version
D0 4.12
8 X
11 X
12 X
13 X
14 X
20 X
21 X
27 X
28 X
47 X
53 X
100 X
101 X
102 X
103 X
104 X
105 X
106 X
107 X
108 X
109 X
110 X
111 X
112 X
115 X
12

November 2012

®
Processor 9500 Series Errata Summary
Status
4.13
No Fix CRC Errors With 16-bit CRC
Scalable Memory Buffer Must Not Be Reset Directly by FPGA or Other System
No Fix
Logic On Warm Reset
No Fix R_CSR_OPER0.PHYTRAINLIMIT Is Not Asserted When All Clocks Fail
No Fix Frame Alert Logged After Warm-Logic Reset
No Fix Bad Parity In Route Table Can Cause Unexpected Error
No Fix Physical Damage To Intel
Northbound Intel
No Fix
Resulting In Fast Reset Loop
North Bound Link Errors Followed Immediately By Erasure+1 Errors Can
No Fix
Cause Correctable Error To Be Uncorrectable
No Fix Corrupted ALERT Frame Not Detected By Zbox
Firmware Setting Z_CSR_FBD_FAIL_CHIP_STATE_[3-0]. chipFailEnable[3-0]
No Fix
During Erasure Can Cause Uncorrectable ECC Error
®
Intel QPI State Machine Does Not Increment On Every Initialization Failure
No Fix
Instance
®
No Fix Intel SMIPbox Does Not Drop Lanes Without Termination on Intel
No Fix FPU Denormal SWA Priority Change
PAL_PERF_MON_INFO Has Implementation Specific Requirements For cycles
No Fix
And retired
®
No Fix Intel QPI State PHY_RESET / PHY_REINIT Not Supported
No Fix Execution Trace Buffer Does Not Record Target Address Of rfi
No Fix Execution Trace Buffer Logs Wrong Source IP On Asynchronous Event
®
Intel QPI Dynamic Link Width Reduction May Result In Quarter Width Mode
No Fix
When Half Width Mode Is Expected
IIP or XIP May Be Invalid Following An Error Reset When An Asynchronous
No Fix
Firmware Interruption Occurs
Transient NB link CRC Error With Consecutive Reads That Contain ECC Errors
No Fix
Can Cause Uncorrectable ECC Error
No Fix Timeout Can Occur With Mirroring Or Migration
®
No Fix Intel QPI Alternate Clock Mode Can Result In Flit Errors During PHY Reset
®
Intel QPI Alternate Clock Mode Does Not Initialize Consistently Due To
No Fix
Noise
®
No Fix Intel SMI Alternate Clock Mode Is Not Supported On The Processor
Fixed Missing Thread After Error Reset
Sighting Title
®
SMI Lane Can Cause Training To Fail
®
SMI CRC Persistent Error Can Cause South Bound CRCs
§
® ®
Intel Itanium Processor 9300 Series and 9500 Series
®
QPI
Specifiication Update