Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Specification page 13

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Intel Itanium
Series Errata
Note: In this section, the Intel
processor".
1. Configuration Agent Responds With Poison Error To Nonaligned
Writes with Poison Set
Problem: When a zero byte request (zero byte error) happens in the same packet with poison for
flit 0 set, the configuration agent (Ubox) responds with a poisoned data error. This
poisoned data error can be identified by U_CSR_SESR.e[9] set to 1.
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Implication: Intel QuickPath Interconnect agents must never issue nonaligned or zero length
writes with poison to the configuration agent (Ubox).
Workaround: None at this time.
Status: No Fix.
2. Hold of Incoming PTC.G Pending During PAL-based IA-32 Execution
Can Cause Deadlock
Problem: A hold of an incoming PTC.G pending during a PAL-based IA-32 execution can cause a
deadlock.
Implication: Deadlock conditions in some code sequences involving PAL-based IA-32 execution and
PTC.G can occur if workaround is not applied.
Workaround: Contact your Intel technical representative for details on workaround.
Status: No Fix.
3. Error During Intel
Problem: An error during link initialization can cause an Intel
timeout and lead to a system hang.
Implication: If this condition is encountered, a hang during Intel
initialization can occur.
Workaround: Firmware can poll Px[n]_PBOXMSCCTL.NO_RESPONSE_FROM_LL. If firmware finds this
bit is asserted it can trigger a reset in the phy layer.
Status: No Fix.
4. Bbox Violates Message Class Dependency
Problem: The Intel
dependency. The Ubox has this dependency since the NCB and NCS share the same
DRS credits. There is also a DRS to NCB dependency at the home agent in mirroring
mode. Logic has been added to the Rbox to prevent this deadlock. Since this logic does
not apply across a Node Controller, mirroring across a Node Controller is not supported.
Implication: Mirroring across a Node Controller is not supported.
Workaround: None at this time.
Status: No Fix.
5. CDEF Memory Region Coherency
Problem: Due to a coherency issue with the CDEF region, if this region is enabled SAL must
ensure the CDEF region has RdEn = 0 and WrEn = 0 in the SAD I/O Decoder if multiple
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Intel Itanium Processor 9300 Series and 9500 Series
Specification Update
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Processor 9300
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Itanium
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QPI Link Initialization Can Cause Hang
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QuickPath Interconnect Specification does not allow an NCB to DRS
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Processor 9300 Series will be referred to as "the
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QuickPath Interconnect link to
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QuickPath Interconnect
November 2012
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