Epson DLQ-3000 Service Manual page 39

Reverse Channel
Y
Transmission mode
Y
Adaptable connector
Y
Synchronization
Y
Handshaking
Y
Data transmission timing
Y
Signal level
Table 1-26 shows the connector pin assignment and signals for reverse channel of the
parallel interface.
Table 1-26. Connector Pin Assignment and Signals (Reverse Channel)
Pin No. Signal Name
1 HostClk
2-9 DATA 1-8
10 PtrClk
PtrBusy /
11
Data bit 3,7
AckDatareq /
12
Data Bit 2,6
13 Xflag/Data bit
1,5
14 HostBusy
31 /INIT
/Data Avail /
32
Data bit 0,4
36 1284-Active
18 Logic-H
35 +5V
17 Chassis GND
16,33,
GND
19-30
15,34 NC
Note)
1. */* at the beginning of a signal means active low.
2. The I/O column indicates the direction of the signal as viewed form the printer.
Rev. A
IEEE-1284 nibble mode
Same as for the forward channel
Refer to the IEEE-1284 specification
Refer to the IEEE-1284 specification
Refer to the IEEE-1284 specification
IEEE-1284 level 1 device
See the forward channel.
Return
I/O
GND Pin
19 I Clock signal from the host computer.
These signals represent parallel data
on bits 2 to 9. Each signal is High
20-27 I
when the data is logical 1 and LOW
when the data is logical 0.
28 O Clock signal from the printer
Busy signal from the printer.
29 O
Data bit 3 or 7 in reverse channel.
Acknowledge request signal.
28 O
Data bit 2 or 6 in reverse channel.
X flag signal.
28 O
Data bit 1 or 5 in reverse channel.
30 I Busy signal from the host computer
30 I Not used
Data available signal.
29 O
Data bit 0 or 4 in reverse channel.
30 I 1284 active signal.
Pulled up to +5V via 3.9 K-ohm
O
resistor.
Pulled up to +5V via 3.3 K-ohm
O
resistor.
Chassis ground for the printer.
Signal ground.
Not connected.
Product Description
Description
1-31