HP Xw6400 - Workstation - 4 GB RAM Reference Manual page 188

Table H-1 PCI device list (continued)
Bus#
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
M(16)
P(30)
P(30)
178 Appendix H Appendix H — PCI bus layout
Dev# Fn#
6 0 Port 6, slave port of port 4
7 0 Port 7, slave port of port 4
8 0 Crystal beach DMA controller (unused, hidden)
9 0 Advanced memory buffer memory-mapped registers (visible via
JTAG/SMBus only)
16 0 FSB controller, interrupt and system address registers
16 1 Address mapping, memory control, error logs
16 2 FSB error registers
17 0 Coherency engine and data manager registers
19 0 Debug and miscellaneous registers
21 0 FBD branch 0 memory map, error flag/mask, and channel control
registers
22 0 FBD branch 1 memory map, error flag/mask, and channel control
registers
27 0 High definition audio controller
28 0 Port 1 PCI Express x4 to slot 2 (secondary bus: 8)
28 1 (PCI Express port 2, hidden)
28 2 (PCI Express port 3, hidden)
28 3 (PCI Express port 4, hidden)
29 0 USB UHCI controller #1
29 1 USB UHCI controller #2
29 2 USB UHCI controller #3
29 3 USB UHCI controller #4
29 7 USB 2.0 EHCI controller
30 0 PCI to PCI bridge (secondary bus: 1, to slot 5 and 6)
30 2 AC97 audio controller
31 0 LPC controller
31 1 IDE controller
31 2 SATA controller
31 3 SMBus controller
4 x Slot 5 (PCI)
9 x Slot 6 (PCI)
0 0 PCI Express upstream port (secondary bus: P)
0 0 PCI Express downstream port E1 (secondary bus: Q) to slot 4
(x8')
1 0 PCI Express downstream port E2 (secondary bus: NIC) to LOM
Device#
ENWW