Constraints for FCIP fastwrite and tape pipelining
Consider the constraints described in
Table 97
Using FCIP fastwrite and tape pipelining
FCIP fastwrite
Each GbE port supports up to 2048
simultaneous accelerated exchanges, which
means a total of 2048 simultaneous
exchanges combined for fastwrite and tape
pipelining.
Does not affect FICON traffic
FCIP fastwrite and FC fastwrite are mutually
exclusive.
Does not support multiple equal-cost path
configurations (see
pipelining
configurations" on page 422).
Class 3 traffic is accelerated with fastwrite.
FCIP fastwrite/tape pipelining configurations
To help understand the supported configurations, consider the configurations shown in the two figures
below. In both cases, there are no multiple equal-cost paths. In the first figure, there is a single tunnel with
fastwrite and tape pipelining enabled. In the second figure, there are multiple tunnels, but none of them
create a multiple equal-cost path.
422 Configuring and monitoring FCIP extension services
Table 97
"FCIP fastwrite/tape
when configuring tunnels to use either of these features.
Tape pipelining
Each GbE port supports up to 2048
simultaneous accelerated exchanges, which
means a total of 2048 simultaneous
exchanges combined for fastwrite and tape
pipelining.
Does not affect FICON traffic
Tape pipelining uses FCIP fastwrite, not FC
fastwrite.
Does not support multiple equal-cost path
configurations or multiple non-equal-cost path
configurations (see
"FCIP fastwrite/tape
pipelining
configurations" on page 422).
Class 3 traffic is accelerated between host
and sequential device.
With sequential devices (tape drives), there
are 1024 initiator-tape (IT) pairs per GbE
port, but 2048 initiator-tape-LUN (ITL) pairs
per GbE port. The ITL pairs are shared among
the IT pairs. For example:
Two ITL pairs for each IT pair as long as the
target has two LUNs.
If a target has 32 LUNs, 32 ITL pairs for IT
pairs. In this case, only 64 IT pairs are
associated with ITL pairs.
The rest of the IT pairs are not associated to
any ITL pairs, so no tape pipelining is
performed for those pairs. By default, only
fastwrite-based acceleration is performed on
the unassociated pairs.
Does not support multiple non-equal-cost path
between host and sequential device