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Table 9.
CMOS Signal Group DC Specifications
Symbol
Parameter
V
I/O Voltage
CCP
V
Input High Voltage
IH
V
Input Low Voltage CMOS
IL
V
Output High Voltage
OH
V
Output Low Voltage
OL
I
Output High Current
OH
I
Output Low Current
OL
I
Input Leakage Current
LI
C
Pad Capacitance
PAD1
C
Pad Capacitance for CMOS Input
PAD2
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The V
referred to in these specifications refers to instantaneous V
CCP
3.
Refer to the processor I/O Buffer Models for I/V characteristics.
4.
Measured at 0.1*V
5.
Measured at 0.9*V
6.
For Vin between 0 V and V
7.
C
includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are included.
PAD1
8.
C
includes die capacitance for all other CMOS input signals. No package parasitics are included.
PAD2
Table 10.
Open Drain Signal Group DC Specifications
Symbol
Parameter
V
Output High Voltage
OH
V
Output Low Voltage
OL
I
Output Low Current
OL
I
Output Leakage Current
LO
C
Pad Capacitance
PAD
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Measured at 0.2 V.
3.
V
is determined by value of the external pull-up resistor to V
OH
details.
4.
For Vin between 0 V and V
5.
C
includes die capacitance only. No package parasitics are included.
PAD
28
0.7*V
0.9*V
.
CCP
.
CCP
. Measured when the driver is tristated.
CCP
V
CCP
.
OH
Min
Typ
1.00
1.05
V
CCP
CCP
-0.10
0.00
V
CCP
CCP
-0.10
0
1.5
1.5
1.6
2.1
0.95
1.2
CCP
Min
Typ
- 5%
V
CCP
0
16
1.9
2.2
. Please refer to platform design guide for
CCP
§
Electrical Specifications
Max
Unit
Notes
1.10
V
V
+0.1
V
CCP
0.3*V
V
CCP
V
+0.1
V
CCP
0.1*V
V
CCP
4.1
mA
4.1
mA
±100
µA
2.55
pF
1.45
.
Max
Unit
Notes
V
+ 5%
V
CCP
0.20
V
50
mA
±200
µA
2.45
pF
Datasheet
1
2
2, 3
2
2
5
4
6
7
8
1
3
2
4
5
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