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Electrical Specifications
Table 4.
FSB Pin Groups (Sheet 2 of 2)
Signal Group
AGTL+ Strobes
CMOS Input
Open Drain Output
Open Drain I/O
CMOS Output
CMOS Input
Open Drain Output
FSB Clock
Power/Other
NOTES:
1.
Refer to
2.
In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
BPM[2:1]# and PRDY# are AGTL+ output only signals.
4.
PROCHOT# signal type is open drain output and CMOS input.
5.
On die termination differs from other AGTL+ signals, please refer to your Platform Design
Guidelines for up-to-date recommendations.
6.
When paired with a chipset limited to 32-bit addressing, A[35:32] should remain
unconnected.
3.8
CMOS Signals
CMOS input signals are shown in
AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for at least three BCLKs in order for
the processor to recognize them.
3.9
Maximum Ratings
Table 5
specifies absolute maximum and minimum ratings. If the processor stays within
the defined functional operation limits, functionality and long-term reliability can be
expected.
Caution:
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected.
Warning:
Precautions should always be taken to avoid high static voltages or electric fields.
Datasheet
Type
Synchronous
to BCLK[1:0]
Asynchronous
Asynchronous FERR#, IERR#, THERMTRIP#
Asynchronous PROCHOT#
Asynchronous PSI#, VID[6:0], BSEL[2:0]
Synchronous
to TCK
Synchronous
to TCK
Clock
Chapter 4
for signal descriptions and termination requirements.
Table
Signals
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#,
STPCLK#
4
TCK, TDI, TMS, TRST#
TDO
BCLK[1:0]
2
COMP[3:0], DBR#
, GTLREF, RSVD, TEST2,
TEST1, THERMDA, THERMDC, V
V
, V
, V
CC_SENSE
SS
SS_SENSE
4. Legacy output FERR#, IERR# and other non-
1
, V
, V
,
CC
CCA
CCP
23
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