Table 8. Diagnostic Led Post Code Decoder - Intel SR2520SAFRNA - Server System - 0 MB RAM User Manual

Checkpoint
Host Processor
0x10h
0x11h
0x12h
0x13h
Chipset
0x21h
Memory
0x22h
0x23h
0x24h
0x25h
0x26h
0x27h
0x28h
76

Table 8. Diagnostic LED POST Code Decoder

Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB
OFF OFF OFF
OFF OFF OFF
OFF OFF G
OFF OFF G A
OFF OFF R G
OFF OFF A
OFF OFF A
OFF G R OFF
OFF G R
OFF G A
OFF G A
G OFF R OFF
LSB
R Power-on initialization of the host processor
(bootstrap processor)
A Host processor cache initialization (including AP)
R Starting application processor initialization
SMM initialization
Initializing a chipset component
OFF Reading configuration data from memory (SPD
on DIMM)
G Detecting presence of memory
Programming timing parameters in the memory
controller
G Configuring memory parameters in the memory
controller
OFF Optimizing memory controller settings
G Initializing memory, such as ECC init
Testing memory
®
Intel Server System SR2520SA User's Guide
Description