Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 52

4. A breakpoint occurs due to either a data breakpoint on the preceding instruction or a
code
Due to this erratum a non-enabled breakpoint triggered on step 1 or step 2 may be
reported in B0-B3 after the breakpoint occurs in step 4.
Due to this erratum, B0-B3 bits in DR6 may be incorrectly set for non-enabled
Implication:
breakpoints
Workaround: Software should not execute a floating point instruction directly after a MOV SS or POP
SS instruction
Status: For the steppings affected, see the Summary Tables of Changes.
AZ76. A 64-bit register IP-relative instruction may Return unexpected Results
Under an unlikely and complex sequence of conditions in 64-bit mode, a register IP-
Problem:
Relative instruction may be incorrect.
A register IP-relative instruction result may be incorrect and could cause software to read
Implication:
from or write to an incorrect memory location. This may result in an unexpected page fault
or unpredictable system behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes
AZ77. Intel Trusted Execution Technology ACM Revocation
SINT ACM GM45_GS45_PM45_SINIT_21.BIN or Earlier are revoked and will not launch
Problem:
with the processor configuration information.
Due to this erratum,
Implication:
revoked.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
software must use SINT ACM GM45_GS45_PM45_SINIT_51.BIN or later.
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breakpoint on the next instruction.
SINT ACM GM45_GS45_PM45_SINIT_21.BIN and earlier will be
All Intel TXT enabled
§
Errata
Specification Update