Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 28

AZ17. Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May Be Incorrect
When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in
Problem:
the MCA address register (MCi_ADDR). Under some scenarios, the address reported may
be incorrect.
Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC
Implication:
errors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ18. Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions
Normally, when the processor encounters a Segment Limit or Canonical Fault due to code
Problem:
execution, a #GP (General Protection Exception) fault is generated after all higher
priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume
from System Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher priority
Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug break (#DB),
Machine Check (#MC), etc.)
Operating systems may observe a #GP fault being serviced before higher priority
Implication:
Interrupts and Exceptions. Intel has not observed this erratum on any commercially
available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ19. Store Ordering May be Incorrect between WC and WP Memory Type
According to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual,
Problem:
Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the
WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores
do. Due to this erratum, WP stores may not drain the WC buffers.
Memory ordering may be violated between WC and WP stores.
Implication:
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
28
Errata
Specification Update