Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 34

AZ32. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that occur
Problem:
above the 4G limit (0ffffffffh) may not signal a #GP fault.
When such memory accesses occur in 32-bit mode, the system may not issue a #GP
Implication:
fault.
Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the 4-
G limit (0ffffffffh).
Status: For the steppings affected, see the Summary Tables of Changes.
AZ33. An Asynchronous MCE during a Far Transfer May Corrupt ESP
If an asynchronous machine check occurs during an interrupt, call through gate, FAR RET
Problem:
or IRET and in the presence of certain internal conditions, ESP may be corrupted.
If the MCE (Machine Check Exception) handler is called without a stack switch, then a
Implication:
triple fault will occur due to the corrupted stack pointer, resulting in a processor
shutdown. If the MCE is called with a stack switch, e.g., when the CPL (Current Privilege
Level) was changed or when going through an interrupt task gate, then the corrupted
ESP will be saved on the new stack or in the TSS (Task State Segment), and will not be
used.
Workaround: Use an interrupt task gate for the machine check handler.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ34. CPUID Reports Architectural Performance Monitoring Version 2 Is
Supported, When Only Version 1 Capabilities Are Available
CPUID leaf 0Ah reports the architectural performance monitoring version that is available
Problem:
in EAX[7:0]. Due to this erratum CPUID reports the supported version as 2 instead of 1.
Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in comparison
Implication:
to which features are actually supported.
Workaround: Software should use the recommended enumeration mechanism described in the
Architectural Performance Monitoring section of the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3: System Programming Guide.
Status: For the steppings affected, see the Summary Tables of Changes.
34
Errata
Specification Update