Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 36

AZ38. Instruction Fetch May Cause a Livelock during Snoops of the L1 Data
Cache
A livelock may be observed in rare conditions when instruction fetch causes multiple level
Problem:
one data cache snoops.
Due to this erratum, a livelock may occur. Intel has not observed this erratum with any
commercially available software.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ39. Use of Memory Aliasing with Inconsistent Memory Type May Cause a
System Hang or a Machine Check Exception
Software that implements memory aliasing by having more than one linear addresses
Problem:
mapped to the same physical page with different cache types may cause the system to
hang or to report a machine check exception (MCE). This would occur if one of the
addresses is non-cacheable and used in a code segment and the other is a cacheable
address. If the cacheable address finds its way into the instruction cache, and the non-
cacheable address is fetched in the IFU, the processor may invalidate the non-cacheable
address from the fetch unit. Any micro-architectural event that causes instruction restart
will be expecting this instruction to still be in the fetch unit and lack of it will cause a
system hang or an MCE.
This erratum has not been observed with commercially available software.
Implication:
Workaround: Although it is possible to have a single physical page mapped by two different linear
addresses with different memory types, Intel has strongly discouraged this practice as it
may lead to undefined results. Software that needs to implement memory aliasing should
manage the memory type consistency.
Status: For the steppings affected, see the Summary Tables of Changes.
36
Errata
Specification Update