Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 50

AZ69. Enabling PECI via the PECI_CTL MSR Incorrectly
Writes CPUID_FEATURE_MASK1 MSR
Writing PECI_CTL MSR (Platform Environment Control Interface Control Register) will not
Problem:
update the PECI_CTL MSR (5A0H), instead it will write to the VMM Feature Flag Mask
MSR (CPUID_FEATURE_MASK1, 478H).
Due to this erratum, PECI (Platform Environment Control Interface) will not be enabled
Implication:
as expected by the software. In addition, due to this erratum, processor features
reported in ECX following execution of leaf 1 of CPUID (EAX=1) may be
masked. Software utilizing CPUID leaf 1 to verify processor capabilities may not work as
intended.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Do not initialize PECI
before processor update is loaded. Also, load the processor update as soon as possible
after RESET, as documented in the RS – Wolfdale Processor Family Bios Writers Guide,
Section 14.8.3 Bootstrap Processor Initialization Requirements.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ70. Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
During the transition from real mode to protected mode, if an SMI (System Management
Problem:
Interrupt) occurs between the MOV to CR0 that sets PE (Protection Enable, bit 0) and the
first far JMP, the subsequent RSM (Resume from System Management Mode) may cause
the lower two bits of CS segment register to be corrupted.
The corruption of the bottom two bits of the CS segment register will have no impact
Implication:
unless software explicitly examines the CS segment register between enabling protected
mode and the first far JMP. Intel® 64 and IA-32 Architectures Software Developer's
Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching
to Protected Mode" recommends the far JMP immediately follows the write to CR0 to
enable protected mode. Intel has not observed this erratum with any commercially
available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ71. The XSAVE Instruction May Erroneously Set Reserved Bits in the
XSTATE_BV Field
XFEATURE_ENABLED_MASK bits [63:9] of register (XCR0) are reserved and must be 0;
Problem:
consequently the XSAVE instruction should not modify the corresponding bits of the
XSTATE_BV field in the header of the XSAVE/XRSTOR area. Due to this erratum, a logical
processor may erroneously write 1 to one or more of these reserved bits.
Software may not operate correctly if it relies on the XSAVE instruction not to modify
Implication:
bits [63:9] of the XSTATE_BV field in the header of the XSAVE/XRSTOR area.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
50
Errata
Specification Update