Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 31

Errata
AZ24. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to
48
2 May Terminate Early
In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count
Problem:
greater than or equal to 2
the following.
 The last iteration not being executed
 Signaling of a canonical limit fault (#GP) on the last iteration
While in 64-bit mode, with count greater or equal to 248, repeat string operations
Implication:
CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel has
not observed this erratum with any commercially available software.
Workaround: Do not use repeated string operations with RCX greater than or equal to 2
Status: For the steppings affected, see the Summary Tables of Changes.
AZ25. Writing the Local Vector Table (LVT) When an Interrupt Is Pending May
Cause an Unexpected Interrupt
If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
Problem:
on the new interrupt vector even if the mask bit is set.
An interrupt may immediately be generated with the new vector when a LVT entry is
Implication:
written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service
Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an
End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector does
not generate an EOI, therefore the spurious vector should not be used when writing the
LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
Specification Update
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may terminate early. Early termination may result in one of
48
.
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