Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 24

AZ7. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
When a performance monitoring counter is configured for PEBS (Precise Event Based
Problem:
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS
buffer. The information in the PEBS record represents the state of the next instruction to
be executed following the counter overflow. Due to this erratum, if the counter overflow
occurs after execution of either MOV SS or STI, storage of the PEBS record is delayed by
one instruction.
When this erratum occurs, software may observe storage of the PEBS record being
Implication:
delayed by one instruction following execution of MOV SS or STI. The state information
in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ8. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts
Problem:
transitions from x87 Floating Point (FP) to MMX™ technology instructions. Due to this
erratum, if only a small number of MMX instructions (including EMMS) are executed
immediately after the last FP instruction, a FP to MMX technology transition may not be
counted.
The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
Implication:
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ9. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent
Triggering of the Monitoring Hardware
The MONITOR instruction is used to arm the address monitoring hardware for the
Problem:
subsequent MWAIT instruction. The hardware is triggered on subsequent memory store
operations to the monitored address range. Due to this erratum, REP STOS/MOVS fast
string operations to the monitored address range may prevent the actual triggering store
to be propagated to the monitoring hardware.
A logical processor executing an MWAIT instruction may not immediately continue
Implication:
program execution if a REP STOS/MOVS targets the monitored address range.
Workaround: Software can avoid this erratum by not using REP STOS/MOVS store operations within
the monitored address range.
Status: For the steppings affected, see the Summary Tables of Changes.
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Errata
Specification Update