Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update page 19

Summary Tables of Changes
Steppings
Number
C-0 M-0
AZ60 X X
AZ61 X X
AZ62
AZ63
AZ64
AZ65 X X
AZ66
AZ67 X X
AZ68
AZ69
AZ70 X X
AZ71
AZ72
AZ73 X X
AZ74
AZ75 X X
AZ76 X X
AZ77 X X
Number
There are no Specification Changes in this Specification Update revision
Specification Update
Status
E-0 R-0
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X No Fix
SPECIFICATION CHANGES
Thermal Interrupts are Dropped During and While Exiting
Intel® Deep Power-Down State
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
VM Entry May Use Wrong Address to Access Virtual-APIC
Page
INIT Incorrectly Resets IA32_LSTAR MSR
When a CPUID instruction is executed, the returned EAX,
EBX, ECX, and/or EDX may be incorrect.
Global Instruction TLB Entries May Not be Invalidated on a
VM Exit or VM Entry
XRSTOR Instruction May Cause Extra Memory Reads
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
Enabling PECI via the PECI_CTL MSR Incorrectly
Writes CPUID_FEATURE_MASK1 MSR
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
The XSAVE Instruction May Erroneously Set Reserved Bits
in the XSTATE_BV Field
Store Ordering Violation When Using XSAVE
Memory Ordering Violation With Stores/Loads Crossing a
Cacheline Boundary
The XRSTOR Instruction May Fail to Cause a General-
Protection Exception
B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be
Incorrectly Set
A 64-bit Register IP-relative Instruction May Return
Unexpected Results
Intel® Trusted Execution Technology ACM Revocation
ERRATA
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